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1. PCIE scanning process

From pressing the PC power button, BIOS will take over the control of the system and begin to work. It will first initialize some memory and devices (of course, including PCI devices). Due to commercial reasons, the BIOS code of Phoenix and other manufacturers need authorization agreements. Here is another open source BIOS (openbios) as an example to analyze how PCIe devices are found and initialized in BIOS.

The scanning of PCI devices is based on the depth-first search algorithm (DFS:Depth First Search), that is, the PCI bridge with the largest number of subordinate branches will be the first to complete the scanning of its child devices. Here is a picture to illustrate how BIOS completes the scanning of PCI devices step by step.

Step 1: the PCI Host main bridge scans the devices on Bus 0 (in a processor system, the PCI bus that is usually directly connected to the HOST main bridge is named PCI Bus 0). The system will first ignore the devices on Bus 0 such as D1 and D2, which will not be connected to the PCI bridge. After the main bridge discovers Bridge 1, the PCI Bus under Bridge1 will be set as Bus 1, and the system will initialize the configuration space of Bridge1. The Primary Bus Number and Secondary Bus Number registers of the bridge are set to 0 and 1 respectively to show that the upstream bus of Bridge1 is 0 and the downstream bus is 1. Because it is impossible to determine the specific conditions of mounting devices under Bridge1, the system temporarily sets Subordinate Bus Number to 0xFF. As shown in figure 1.1:

Figure 1.1 the first step of PCIE scanning

Step 2: the system starts scanning Bus 1 and will find Bridge 2. The system sets the PCI Bus under Bridge 2 as Bus 2, sets the Primary Bus Number and Secondary Bus Number registers of the bridge to 1 and 2 respectively, and temporarily sets the Subordinate Bus Number of Bridge 2 to 0xFF as in the previous step. As shown in figure 1.2:

Figure 1.2 PCIE scan step 2

Step 3:

The system continues to scan Bus 2 and will find Bridge 4. The system sets the PCI Bus under Bridge 4 as Bus 3, and sets the Primary Bus Number and Secondary Bus Number registers of the bridge to 2 and 3, respectively.

After the system continues to scan, it is found that there is no Bridge under Bus 3, which means that there is no downstream bus mounted under the PCI bus, so the Subordinate Bus Number value of Bridge 4 can be determined to be 3.

As shown in figure 1.3:

Figure 1.3 PCIE scan step 3

Step 4:

After completing the scan of Bus 3, the system returns to Bus 2 to continue the scan and finds that there are no other Bridge under Bus 2. At this point, the value of Subordinate Bus Number for Bridge 2 can also be determined to be 3. As shown in figure 1.4:

Figure 1.4 PCIE scan step 4

Step 5:

After completing the scan of Bus 2, the system returns to Bus1 to continue scanning and finds Bridge 3, and the system sets the PCI Bus under Bridge 3 as Bus 4. The Primary Bus Number and Secondary Bus Number registers of Bridge 4 are set to 1 and 4 respectively. After that, the system continues to scan and finds that there is no Bridge under Bus 4, which means that no downstream buses have been mounted under the PCI bus, so the value of Subordinate Bus Number of Bridge 3 can be determined as 4. As shown in figure 1.5:

Figure 1.5 PCIE scan step 5

Step 6:

After completing the scan of Bus 4, the system returns to Bus 1 to continue the scan and finds that there are no other Bridge under Bus 1. At this point, the value of Subordinate Bus Number for Bridge 1 can be determined to be 4, and the system returns Bus 0 to continue scanning (if there is another Bridge under Bus 0, the above steps will be repeated for scanning). At this point, the device scan for the entire PCI in this example is complete. The scan results of the final device and bus are shown in figure 1.6

Figure 1.6 PCIE scan step 6

Generally speaking, the configuration space of PCI can be accessed through two registers (registers CONFIG_ADDRESS and CONFIG_DATA). In x86 system, these two registers correspond to 0xCF8 and 0xCFC ports respectively. Access to the configuration space is realized by reading and writing these two registers. The specific bit composition of the CONFIG_ADDRESS register is shown in figure 1.7:

Figure 1.7 x86 configuration register

Bus Number: bus number (8 bit), range 0 Murray 255.

Device Number: device number (5 bit), range 0Murray 31.

Function Number: function number (3 bit), range 0Murray 7.

Register Number: register number (6 bit), range 0 Murray 63 (configuration space total of 256 bytes, divided into 64 4-byte registers, numbered from 0Murray 63).

Each PCI device can locate the specific device and access its configuration space according to the four information shown above: Bus Number, Device Number, and Function Number,Register Number. When accessing the configuration space of the PCI device, first set the CONFIG_ADDRESS register according to the above format, and then read the CONFIG_DATA register to get the corresponding value of the configuration space register. Through these steps, BIOS completes the scanning of all PCI devices and allocates system resources to each device.

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