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This article mainly introduces "jk trigger is rising edge or falling edge". In daily operation, I believe many people have doubts about whether jk trigger is rising edge or falling edge. Xiaobian consulted all kinds of data and sorted out simple and easy-to-use operation methods. I hope it will be helpful to answer the question of "jk trigger is rising edge or falling edge". Next, please follow the editor to study!

Not all Jk flip-flops are effective on the falling edge, but whether the falling edge is effective or the upper falling edge is effective is related to the internal structure of the flip-flop. The lower rising edge efficiency means that the state of the flip-flop can only change when the clock signal jumps from high level to low level.

The operating environment of this tutorial: windows7 system, Dell G3 computer.

Triggered by the falling edge, there is a small circle in the CP control signal indicating that the falling edge is valid.

Rising edge efficiency means that the state of the flip-flop can only change when the clock signal changes from low level to high level. Similarly, the lower rising edge efficiency refers to the change of the state of the flip-flop when the clock signal jumps from high level to low level.

In addition, not all Jk flip-flops are effective on the falling edge, and not all D flip-flops are effective on the rising edge, so there is no such a corresponding relationship. Whether the falling edge is effective or the upper falling edge is effective is related to the internal structure of the flip-flop.

JK flip-flop has the functions of setting 0, setting 1, holding and flipping. Among all kinds of integrated flip-flops, JK flip-flop has the most complete functions. In practical application, it not only has strong versatility, but also can flexibly convert other types of triggers. D flip-flop and T flip-flop can be formed by JK flip-flop.

The structure of JK flip-flop is similar to that of RS flip-flop, except that RS flip-flop does not allow R and S to be 1 at the same time, while JK flip-flop allows J and K to be 1 at the same time. When J and K change to 1 at the same time, the value state of the output is reversed. In other words, if it is 0, it becomes 1; if it is 1, it becomes 0.

Extended data

Working characteristics of JK Flip-flop

Establishment time: refers to the time at which the input signal should arrive before the CP signal, expressed as tset. As can be seen from figure 7.5.5, the J and K signals can arrive no later than the CP signal, so there is tset=0.

Hold time: in order to ensure the reliable flip-flop of the trigger, the input signal needs to be maintained for a certain period of time. The hold time is expressed in tH. If the state of J and K during CP=1 is required to remain unchanged, and the time of CP=1 is tWH, then it should be satisfied: tH ≥ tWH.

Transmission delay time: if the time from the beginning of the falling edge of CP to the stable establishment of the new state at the output side is defined as the transmission time, then there is the highest clock frequency of tPLH=3tpd tPHL=4tpd: because the master-slave flip-flop is composed of two synchronous RS flip-flops, the dynamic characteristics of synchronous RS flip-flops can be known.

In order to ensure the reliable flipping of the main flip-flop, the duration of the CP high level tWH should be greater than the 3tpd. Similarly, in order to ensure that the slave trigger can be flipped reliably, the duration of the CP low level tWL should also be greater than the 3tpd. Therefore, the minimum period of the clock signal is: Tc (min) ≥ 6tpd the highest clock frequency fc (max) ≤ 1/6tpd.

At this point, the study on "whether the jk trigger is the rising edge or the falling edge" is over. I hope it can solve everyone's doubts. The collocation of theory and practice can better help you learn, go and try it! If you want to continue to learn more related knowledge, please continue to follow the website, the editor will continue to work hard to bring you more practical articles!

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