Shulou(Shulou.com)06/02 Report--

We learned about makefile earlier, and today we look at the substitution of variable values in makefile. Its replacement refers to replacing the suffix character (string) in the variable value with the specified character (string). The syntax format is: $(var:a=b) or ${var:a=b}. Note: there cannot be any spaces in a > substitution expression; using ${} to value variables is supported in b > make. The format is as follows

Another is that the mode substitution of a variable is to replace other characters with the specified characters in the value of the% reserved variables. The syntax format is: $(var:a%b=x%y) or ${var:a%b=x%y}. Note: there cannot be any spaces in a > substitution expression; using ${} to value variables is supported in b > make. The format is as follows

The pattern substitution in the rule is as follows

Its meaning is to match sub-goals from targets through target-pattern, generate dependencies from sub-goals through prereq-pattern, and then form complete rules. Let's take a look at the pattern substitution examples in the rules as follows

Let's analyze and explain through the code.

Src1: = a.cc b.cc c.ccobj1: = $(src1:cc=o) test1: @ echo "obj1 = > $(obj1)" src2: = a11b.c a22b.c a33b.cobj2: = $(src2:a%b.c=x%y) test2: @ echo "obj2 = > $(obj2)"

According to what we said earlier, we will replace .cc with .o in obj1 and a11b.c a22b.c a33b.c with x11y x22y x33y in obj2. Let's take a look at the compiler effect.

We see that the results are the same as those we analyzed. Let's take a look at the pattern replacement, adapting the previous makefile.

CC: = g++TARGET: = hello-makefile.outOBJS: = func.o main.o$ (TARGET): $(OBJS) $(CC)-o $@ $^ $(OBJS):% .o:% .c $(CC)-o $@-c $^ .PHONY: rebuild clean allrebuild: clean allall: $(TARGET) clean: $(RM) * .o $(TARGET)

Let's see if the compilation effect is the same as before?

The result is the same, what is the meaning of such writing? In large-scale engineering projects,. C source files are thousands. We can use pattern substitution instead of repetitive work. For example, if we want to add a const.c file, we can add const.o and OK directly to line 3. Let's try it.

Const.c source code

Const char* g_hello = "hello makefile"

Func.c source code

# include "stdio.h" extern char* foo () {printf ("void foo ():% s\ n", g_hello);}

Main.c source code

Extern void foo (); int main () {foo (); return 0;}

Let's take a look at the compilation effect.

We see that the command to compile const.c is automatically added during compilation, and the result is printed correctly. Isn't it convenient to feel like this? Then in makefile, variable values can also be nested references, that is, a variable name can contain references to other variables, and the essence of nested references is to use one variable to represent another variable. The format is as follows

Let's talk about command-line variables, which are defined directly on the command line when you run make. Command line variables override the variables defined in makefile by default in the following format

So command-line variables can override variables defined in makefile. What if we accidentally override them? That's when the override keyword came out. It is used to indicate that variables defined in makefile cannot be overridden, and the definition and assignment of variables requires the use of the override keyword. The format is as follows

Let's take a look at the define keyword in makefile, which is used to define multiline variables in makefile. The definition of multiline variables starts with the variable name and ends with endef. You can use the override keyword to prevent variables from being overwritten, and variables defined by define are equivalent to variables defined with =. Format down

Let's take the code as an example.

Hm: = hello makefileoverride var: = override-testdefine fooI'm foolendedfoverride define cmd @ echo "run cmd ls." @ lsendeftest: @ echo "hm = > $(hm)" @ echo "var = > $(var)" @ echo "foo = > $(foo)" ${cmd}

Let's compile and see the results.

We can see that the variable hm that is not modified by the override keyword can be rewritten on the command line, but the variable cmd is modified by override, so the modification on the command line is invalid. Let's also talk about environment variables (global variables) in makefile, where you can use the values of environment variables directly in makefile. It is that if a variable with the same name is defined, the environment variable will be overridden, specify the "- e" option when running make, and give priority to the environment variable. So why use environment variables in makefile? Its advantage is that environment variables can be used in all makefile, while the disadvantage is that relying too much on environment variables will lead to reduced portability. So what are the ways in which variables are transmitted in different makefile stents? A > define environment variables directly for passing; b > use export to define variables for passing; c > define make commands for passing (this is generally recommended).

Let's take the code as an example to analyze it.

Export var: = D.T.Softwarenew: = TDelphitest: @ echo "make another file..." @ $(MAKE)-f makefile.4 @ $(MAKE)-f makefile.4 new:=$ (new)

Makefile.4 source code

Test: @ echo "var = > $(var)" @ echo "new = > $(new)"

Let's take a look at the compilation results.

We see that the new is empty the first time, and the string new set for us the second time. Both var were passed because we used the keyword export. Let's take a look at the target variable (local variable), whose scope is only in the specified target and associated rules. The format is as follows

Then the schema variable is an extension of the target variable, and its scope is only in the target and associated rules that conform to the pattern. The format is as follows

Let's take the code as an example to analyze and illustrate.

Var: = D.T.Softwarenew: = TDelphitest: var: = test-var%e: override new: = test-newtest @ echo "test:" @ echo "var = > $(var)" @ echo "new = > $(new)" another: @ echo "var = > $(var)" @ echo "new = > $(new)" rule: @ echo "rule:" @ echo "var = > $(var)" @ echo "new = > $(new)"

Let's take a look at the compilation results.

Because of the matching rule of% e, in the target rule, its new is test-new, and any var associated with the test target is test-var. Through the study of variables in makefile, the conclusions are as follows: 1. Variable values in makefile can be nested references; 2. Variables defined on the command line can override variables defined in makefile; 3. Override is used to prompt variables defined in makefile cannot be overridden; 4. Define is used to define variables whose values are multiple lines in makefile. 5. Three kinds of variables in makefile: a > global variable refers to environment variables defined outside makefile B > file variables are variables defined in makefile; c > local variables are variables that specify the target.

Welcome to learn makefile, you can add me QQ:243343083.

Welcome to subscribe "Shulou Technology Information " to get latest news, interesting things and hot topics in the IT industry, and controls the hottest and latest Internet news, technology news and IT industry trends.