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This article introduces the relevant knowledge of "how to use Makefile in Linux system". In the operation of actual cases, many people will encounter such a dilemma, so let the editor lead you to learn how to deal with these situations. I hope you can read it carefully and be able to achieve something!

About 1.Makefile using GNU Make tools to manage programs is a skill that every Linux engineer must master. Make enables the compilation and linking of the whole program to be completed with only one command (make). Make's work relies mainly on a file called Makefile. The Makefile file describes the compilation, connection and other rules of the whole program. These include: which source files in the project need to be compiled and how to compile, and how to finally produce the executable files we want.

2. Makefile composition-the most important component of the rule Makefile is the "rule" rule, which is used to explain how to generate the target file. The format of the rule is as follows: targets: prerequisitescommand target dependent command specially provided: the command needs to use the [TAB] key space.

3. Makefile composition-pseudo-target Makefile refers to those targets that contain only commands and do not have any dependencies as "pseudo-targets" (phony targets). PHONY: cleanclean: rm-f hello main.o func.o ".PHONY" declares "clean" targets as pseudo-targets.

4. Makefile composition-final goal 1. When there are multiple rules in a makefile, how do you execute a rule separately? Make led.o (automatically judge with a target name)\ 2. If the user does not specify a rule to execute, make will execute the first rule in makefile by default, and the goal in this rule is called the final goal

5. Makefile rules-before variables use variables: app1: app1.o func1.o func2.ogcc app1.o func1.o func2.o-o app1app2: app2.o func1.o func2.ogcc app2.o func1.o func2.o-o app2 after using variables: obj=func1.o func2.oapp1: app1.o (obj)-o app1app2: app2.o (obj)-o app2 repeated names that can be expressed as variables. There is no particular type difference. When in use, users can not only define variables themselves, but also use default variables that exist and have been defined by the system. ^: represents all dependent files: represents the target, which is relative to the target name and dependency name, such as led.o:led.S, which is relative to the target name and dependency name, such as led.o:led.S

6. Makefile rules-before variable use: led.o: led.Sarm-linux-gcc-g-o led.o-c led.S after use: led.o: led.Sarm-linux-gcc-g-o ^

7. Makefile composition-General rules when there are many similar rules in a makefile, how do you combine these rules into one general rule? %. O:%. S arm-linux-gcc-g-o kslasjd-o klsdjalkdj3. Tips-the content after echoing the "#" character in Makefile is treated as a comment. Hello: hello.c@gcc hello.c-o hello@:@: cancel echo (demo)

3. Tips-the file name make command looks for a project file named makefile or Makefile in the current directory by default. If the name is not one of the two, you can specify it by using the following method: make-f file name is Makefile file

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