Shulou(Shulou.com)06/01 Report--

It is believed that many inexperienced people do not know what to do about the implementation of the lower board in the reading and writing sequence of mig. Therefore, this paper summarizes the causes and solutions of the problem. I hope you can solve this problem through this article.

This experiment and project are based on the Arty Artix-35T FPGA development board of Digilent.

The software uses Vivado 2018.1.

The realization of mig read and write time sequence under the Board

1 Top-level files and constraint files

Ddr3_test.v

See reference project: ddr3_test.

Ddr3.xdc

Set_property PACKAGE_PIN E3 [get_ports clk]

Set_property IOSTANDARD LVCMOS33 [get_ports clk]

Set_property PACKAGE_PIN D9 [get_ports reset]

Set_property PACKAGE_PIN E1 [get_ports init_calib_complete]

Set_property IOSTANDARD LVCMOS33 [get_ports init_calib_complete]

Set_property IOSTANDARD LVCMOS33 [get_ports reset]

(2) to realize the reading and writing timing on the lower board

1 > ① completes synthesis and implementation

2 > download bit file and debug file.

3 > download is complete, check the waveform.

4 > change the app_wdf_data data format to Unsigned Decimal.

5 > check the writing sequence.

6 > check the reading sequence.

The read and write verification of ddr3 is completed based on xilinx mig ip.

After reading the above, have you mastered the method of how to implement the lower board of mig reading and writing sequence? If you want to learn more skills or want to know more about it, you are welcome to follow the industry information channel, thank you for reading!

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