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This article mainly introduces "what is the basic concept in server timing analysis". In daily operation, I believe that many people have doubts about what is the basic concept in server timing analysis. The editor consulted all kinds of data and sorted out simple and easy-to-use operation methods. I hope it will be helpful for you to answer the doubts about "what are the basic concepts in server timing analysis?" Next, please follow the editor to study!

1. Establish hold time

two。 Four temporal paths

The first type of timing path: from the clock of device A to the data input port of the first stage register of FPGA

The second type of sequential path: the path between two synchronous originals, such as the rega clock port to the data port of regb

The third type of timing path: the path from the last level register clock port to the device B data port

The fourth type of sequential path: the port-to-port path (pure combinational logic, the starting point of the input port to the end of the output port)

3. Timing path selection

Source timing path, data path, destination timing path

4. Data arrival time

The data arrival time reflects how long it takes for the data to reach the receiving register port along the receiving edge after the data is sent along the sending edge.

5. Clock arrival time

Clock arrival time refers to the clock that captures registers (destination registers).

L setup time-the minimum time that data can be captured

Established uncertain time such as jitter

2 hold time-when the data is captured, the data should remain stable for a period of time

3 establish a hold time threshold

For the establishment time, the data arrival time refers to the arrival time of the current data.

For the retention time, the data arrival time refers to the arrival time of the next data.

If Slack is positive satisfying timing constraints.

Else is not satisfied

If the setup time is not satisfied, consider that the data delay is too large.

If the hold time is not satisfied, consider that the clock delay is too large.

Tdata=Tlogic+Tnet (logical delay {code style}, cabling delay {cabling})

Ts ≥ Tco+Tdata+Tsu (these three parameters determine the highest frequency of the system)

Design skills of VIVADO

Xdc: temporal constraints, physical constraints

User-designed file management: src, sim, xdc

Use Manage IP to manage IP (convenient for follow-up applications)

Update IP

1.Reset all IPs

2.Upgrade all IPs

3.Regenerate all IPs

Proc reset_ips {myips} {

Foreach ip $myips {

Reset_target all $ip

Delete_ip_run $ip

}

}

Get constraint compilation file order Tcl:report_compile_order-constraints

Simulation report_compile_order-used_in simulation

Integrated report_compile_order-used_in synthesis

Save captured ila data

Write_hw_ila_data my_hw_ila_data_file.zip [upload_hw_ila_data hw_ila_1]

Read captured ILA data

Displap_hw_ila_data [read_hw_ila_data my_hw_ila_data_file.zip]

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