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In this article, the editor introduces in detail "what are the common problems in Cadence layout and routing?" the content is detailed, the steps are clear, and the details are handled properly. I hope that this article "what are the common problems in Cadence layout and routing" can help you solve your doubts.

1. How to build your own component library?

After establishing a new project, the first step in drawing the schematic diagram is to build the library you need, and the tool used is part developer. First, create a directory where the catalog is stored (such as mylib), then open cds.lib with WordPad and define: Define mylib d:\ board\ mylib (the path where the directory is located). In this way, you set up your own library. In component- > add of Concept_HDL, click search stack to join the library.

2. What is the difference between Save view and Save all view when saving and between choosing Change directory and not selecting it?

When you set up a component library, you should first save it and choose save view as far as possible. In concept-HDL, after we click on the device directly with the left mouse button, we can modify the size of the device. If you enter part developer and make some modifications, if you choose save all view, you will return to the original size and choose save view.

Will retain the changed shape.

3. How to build a part library and how to change the location of pin feet in symbol?

Tools/part developer can be established in project manager, select the library and define part name, add package/addpin in add symbol,package in symbol, and enter pin in turn:

In package:

A, Name: pin's logical name cannot be repeated

B, pin: the label of pin, the corresponding label after backannotate in the schematic

C, pin type: type of pin foot (input,output, etc., can be ignored for the time being)

D, trigger types of active:pin high (high level), low (low level)

E, nc: fill in the label of the empty foot

F, total: the number of all pin feet of this type

G, the following is brief

In symbol:

A, logical name: corresponding to the name in package

B, type: corresponding to type in package

C, position:pin pin position in the device (left, right, top, bottom)

D, the name displayed by pintext:pin in the device (corresponding to the pin in package, but repeatable, such as in package

Both gnd1 and gnd2 can be set to gnd)

E, active: corresponding to active in package

Modify: open the device to be modified with part developer, * Select edit/restrict changes (if not, the device is protected, and save the disk is invalid after modification), general modification:

A, the label and name of the corresponding pin in package

B, active type of pin

C, the order of pin pins in symbol (the order of pin pins will be changed after the first save, for more

Pin pin devices, such as 232pins, are complicated to modify, so try their best to ensure a success rate. The order of pin pins in the device is determined according to the order in symbol, so the order of pin pins in symbol must be correct. If there is an error to modify, select pin and press the ctrl key with the up and down keys to move the pin pin position.

4. Why do Save and packaging go wrong when drawing electrical schematics?

When saving errors, the main reason may be: the signal line drawn may coincide with the pin pin of the component, or the signal line itself coincides; the signal line may be named repeatedly; the signal line may not be named; in the high version (version 14.0 or above), the library you create cannot be the same as the library name that comes with the system itself; when building the library, the number of pins that encapsulate the original is different from that of the original library. The reason for the error when packaging may be that the package type does not match the component (such as the number of pin feet, the type name of the package, etc.).

5. How to modify the device properties and package type in the electrical schematic diagram?

Select the Attribute feature in the menu Text drop-down menu, then click on the device, then an Attribute window pops up, and click the Add button, you can add name, value,JEDEC_TYPE (package type) and other attributes.

6. How to define Pad/via in Pad Design? And how to call * .pad?

In pad design, when establishing a pad, type selects the single type, and the dimensions of the following layers should be defined: begin layer (sometimes end layer), soldermask, and pastemask. When establishing a Via, type generally chooses through to define the size of the drill hole and all the layer layers (note that thermal relief and anti pad are defined) and soldermask. Generally speaking, Pastemask is as big as Regular, soldmask is several Mil larger than layer, and thermal relief and anti pad are larger than regular pad. 10Mil.

7. What should I pay attention to when making a packaging library?

For encapsulation, you can either File- > New- > package symbol in Allegro, or use Wizard (automatically to

Guide) function. In this process, the most important thing is to determine the distance between the pad and the pad (including the adjacent and the corresponding pad) to ensure that the Pin pin of the components can be completely affixed to the Pad in the later packaging process. If you only know the size of Pin, the size of pad should be slightly larger than Pin when designing. Generally, width is 1.2 to 1.5 times larger, and length is about 0.45mm longer. In addition to the size of pad need to pay special attention to, but also add some layers, such as SilkScreen_top and Bottom, because in the future to do light drawing documents need (Goldfinger can not be), Ref Des is also best marked on the Silkscreen layer, while pay attention to screen printing layer do not draw on the Pad. Should also mark the position of the No.1 pin foot, there are some special packages, such as gold finger, you can also add a layer of Via keep out, or route keep out, etc., which can be added according to your own requirements. It should be noted that after the package is built, don't forget to click Create symbol, otherwise the * .psm file will not be generated and cannot be called in Allegro.

8. Why can't I Import Netlist?

Select Import--- > logic in the File option in Allegro and HDL-concept in import logic type. Note that in the Import from column, confirm that it is the packaged directory under the working path. The system may automatically default to the physical directory.

9. How to define your own keyboard shortcuts in Allegro?

In the blank box below allegro, immediately after the command > prompt, type alias F4 (shortcut key) room out (command). Or there is an env file in the Cadence installation directory / share/pcb/text, open it with WordPad, find the part defined by Alias, and modify it manually.

10. How to define the stack? How do I change the stacking settings after the wiring is complete?

In Allegro, select Setup-?Cross-section. If you want to add a layer, select Insert in the Edit field, delete it to del, material type, insulation layer is generally FR-4, Etch layer is Copper, layer type, wiring layer is Conductor, copper layer is Plane, insulation layer is Dielectric,Etch Subclass Name and Top,Gnd,S1,S2,Vcc,Bottom, respectively.

Film Type generally chooses Positive,plane layer and Negative. If you find that the stacking settings need to be changed after the cabling is completed. For example, the plane layer was originally set to 3Jing layer 4, but now it needs to be changed to 2JI layer 5, which cannot be simply changed by renaming. You can first add two plane layers to 2Jing layer 5, and then delete the original plane layer.

11. Why are the components not displayed or displayed in the list in the Allegro layout?

First of all, make sure whether the path of Psmpath,padpath is set, if not, you can set it in Partdevelop, or add it manually in the env file. It is also possible that the device exists in the list, but cannot be called up. You can check whether the * .pad file and the package library file * .dra, * .psm used by the device exist in your working directory * × / physical. Another possibility is that the page is too small to put devices and can be adjusted in setup-?draw size.

12. Why is the position of the device inaccurate and the offset too large?

Mainly because of the problem of Grids setting, the Etch of each layer and the X, Y spacing interval of Non-etch grids can be reduced in setup-grids. For some devices that have strict requirements for position, such as slots, gold fingers and other components used for the interface, they should be located strictly according to the position size given by the designer and coordinate instructions on the command line. For example, x 1200 3000.

13. How to make a Mechanical symbol and how to call it?

File-?new in Allegro, select Mechanical symbol in drawing type. The main purpose is to generate the outer frame model of the PCB board, in which you can also add pad, but there is no pin correspondence. After the Mechanical symbol is complete, the * .dra file is generated. When called in Allgro, select by symbol- > mechanical. Notice the tick in front of the library in the lower right corner.

14. How to get a collated library of all components after layout?

If you think that all kinds of files under the physical directory are too cumbersome and want to delete some useless files, or there is only one * .brd file, and you want to get all the information about the components and the pad wrapper library, you can use this method: store * .brd in a new directory, File- > select export- > libraries, click all the options, and then export, you can generate all the * .brd files in your new directory.

15. How do I define the Rule of the distance between lines?

Let's take defining the distance between the CLK line and other signal lines as an example:

In Allegro: setup- > constraints, click set values in spacing rule set. First add a constraint set name, for example, we call it CLOCK_NET, and then define the specific rules to follow below.

For example, line to line is defined as 10 mil. Then select properties under the edit menu in the main allegro window, which will jump out of your Control toolbar, select net in find by name, and click more in the lower right corner. In the list of new pop-up windows, select the CLK lines you want to specify, such as CK0, CK1, CK2, etc., make sure that all the lines are selected in the selected objects on the right, and click Apply. A new window will appear, select NET_SPACING_TYPE in the available properties on the left, and assign it a value (random name) on the left, such as CLK. Go back to setup- > constraints

Click Assignment table under set values just now to assign the defined rules to the selected net.

In Specctra, you can first select the signal line that you want to define the spacing (select-> nets- > by list), and then select selected net- > clearance in rules. A series of routing rules can be defined in this window. For example, to define the spacing between lines, you can define it in the wire-wire bar. Note that when the point Apply or OK, the bar still displays-1 (meaning unlimited), just look at the blank bar at the bottom of the screen to see if there is a defined message prompt.

16. Why can't you draw a line in Allegro at a 45-degree angle?

In the line lock of the control control bar, you can change 90 to 45, and if you want to draw an arc, you can change line to Arc.

17. How to define the maximum and minimum distance of alignment in CCT?

Similar to the above method of defining spacing, after selecting the line to be defined, rules- > selected net- > timing, you can define the maximum and minimum length limit of the alignment in minimum length and maximum length, or you can define the time delay as the limit. Another method is to extract the topological structure of a signal line in Specctra Quest as a model, define the length limit of each wire, and then generate a rule file, which can constrain the alignment of the same type of signal line.

18. How to save and read disk (color setting, rule saving) in CCT?

In Specctra, you can use file- > write- > session to save the current wiring, use file- > write- > rules did files to save the rule file, use file- > execute do file when calling, and then type the save file that needs to be called, such as Initial.ses or rules.rul. Use write colormap and load colormap in color palette to save and read color settings.

19. How to roughly define the position of automatic drilling in CCT, how to punch a row of holes and define its arrangement shape?

There is a function of automatic drilling in CCT, in Autoroute- > Pre Route- > Fanout. You can specify the direction of the hole. For example, if you want to punch all the holes inside the Pad, you can select inside in the location. Some other restrictions can also be defined. In addition, sometimes we can select a group of lines for parallel alignment, then it is possible to make a row of holes at the same time, right-click the mouse to select set via pattern, you can choose its arrangement shape. There are also shortcut buttons to choose from at the lower right of the window.

20. Why does the maximum and minimum distance of the prompt not change with the length of the line?

After we have defined the rule of the longest and shortest routing, there will be a number display when routing, telling you at any time how much deviation it will be from the defined rule if the wiring is in the current direction. Generally within the regular length of the green font display, more than or not long enough will be displayed in red font, and use + /-prompt deviation. But the deviation of this tip does not simply vary with the length of your line. It is based on your wiring direction, the software automatically calculates the comparison between the length of the line in this direction and the specified length, and it will recalculate if you change the direction of the wiring.

21. How to lay the plane layer? How do I modify it after it is laid?

The step of laying copper must be carried out in Allegro, Add- > shapes- > Solid Fill, and note that in the Control toolbar, select Etch,Subclass to select the Plane layer to be laid, such as VCC or GND. Then draw the frame, notice that there is a spacing of about 20 Mil from the outline. After Done, you will enter the copper laying interface and select Edit- > Change net (by name) to name the Plane layer. Determine whether Anti Pad and Thermal relief are used in shape- > parameters, then select Void- > Auto, the software will automatically detect Thermal relief, after completion, log will report, if there are no errors, you can lay out shape,shape- > Fill. If there are changes through the hole after the paving, and you need to resurface the copper, you should select Edit- > shape, click on shape, and then right-click to select done, so that the Thermal relief connected to the shape will be deleted automatically, and the shape layer of copper cannot be hard deleted, otherwise those Thermal relief will be left on the Plane layer.

22. How to define the line width between the through hole and the shape line in thermal-relief?

The width of each layer can be defined in set standard values in Setup- > constraints of Allegro. For example, the linewidth of VCC and GND can be defined as 10 Mil. When laying copper, pay attention to whether some lineweight definitions in shape- > parameters are set to DRC Value.

23. How to optimize the cabling without changing the overall shape of the cabling?

After the wiring is completed, it needs to be optimized, generally using the system automatic optimization, mainly to change the right angle to 45 degrees, as well as the smoothness of the lines. Route- > gloss- > parameters, in the list that appears, select Line smoothing, Gloss can be, but sometimes the wiring in order to ensure that the alignment distance is equal, deliberately walk into some curved lines, optimization, click on the left side of the Line Smoothing box, only select convert 90s to 45s, the other ticks are removed, so that the designer will not deliberately bend the alignment straightening or deformation.

24. How to add teardrop pads and delete them after adding them?

In the optimized parameters option, only select the penultimate Pad And T Connection Fillet, and remove the Pin option to optimize. If you want to delete, only select dangling Lines in Line smoothing to optimize. Note: if there are no special requirements, we will not do this optimization now.

25. What should I do if I need to change the wrapper library after cabling?

At the end of the device placement, if there is a change in the packaging library, you can Place- > update symbols. If there is a change in pad, please check before update symbol padstacks. After the completion of the wiring, try to avoid changes to the encapsulation library, because if update, the connection to the Pin will move with the Symbol, resulting in the loss of many connections, the specific solutions need to be studied.

26. Why can't * .brd save?

If you encounter this situation, pay attention to the prompt in the blank bar at the bottom of the screen. There may be insufficient hard disk space, or there may be a database error. The software will automatically save the disk as * .SAV file. At this time, you can re-enter Cadence (you may need to restart it), open * .SAV, and save as * .brd. Or run DBFix .SAV under Dos, which is automatically converted to

* .brd file, and then can be called.

What database correction commands does 27.Allegro have under Dos?

Sometimes there will be some illegal overwork in Allegro, resulting in some data errors. We can run some correction commands, such as Dbcheck *. Brd, or Dbfix *. Brd, in the working directory (that is, the physical directory) in Dos mode. But in practice, these commands don't seem to have much effect.

28. How to generate * .DML model library?

In dos mode, under the working directory, type the brd2dml * .brd command, which will generate the model library dml file for the corresponding brd file in that directory.

29. How to use the IBIS model for simulation in Specctra Quest?

First convert the IBIS model to a * .dml file. In Specctra Quest SI expert, Analyze- > Si/EMI SI- > library, in the lower right corner of the new window that appears, click translate- > ibis2signoise, then select the * .ibs file in browse and convert it to a * .dml file. Then load all the devices into the corresponding model in Analyze- > SI/EMI SI- > model Assign. Then you can use probe to extract signal lines for simulation.

30. What files do I need to generate Gerber file? How is it produced?

After the completion of the PCB wiring, the last work done is to generate the light drawing files needed by the manufacturer, and the specific steps are completed under the Allegro tool. Click the Artwork option under the Manufacture menu, and an artwork control form window appears. The photographic file provided includes not only the generated TOP, GND, S1, S2, VCC, BOTTOM6 layers, but also silkscreen_top, silkscreen_botom, soldermask_top, soldermask_bottom, pastemask_top, pastemask_bottom, drill drawing file, and drill hole. Let's take making the top layer of Silkscreen as an example.

1) in the Allegro window, click the color icon, and in the resulting window, global visibility select

All invisibility, turn off all the displays.

2) in group, select Geometry. Then select all subclass (Board_Geometry, package)

Silkscreen_top under Geometry).

3) also select Autosilk_top in Group/ manufacture. Select silkscreen in Group/components, subclass REF DES.

4) Select the OK button and the silkscreen_top layer appears in the Allegro window.

5) in the artwork control form window, right-click Bottom, select add from the drop-down menu, type: silkscreen_top in the window that appears, click O.K, and the newly added silkscreen_top appears in avilibity films.

Note: select Use Aperure Rotation in FILM opition and fill in 5 (or 10) in Underined line width to define the width of lines that do not yet have a lineweight size.

Follow the steps above to generate the silkscreen_ bottom layer. The soldermask_top and soldermask_bottom layers are: Gemoetry group and Stackup group (select PIN and VIA subset); Pastemask_top and Pastemask_bottom are in Stackup group (select PIN and VIA subset); DrillDraw includes Ncdrill_Legend in outline, Dimension and Manufacturing in Group group / Board Geometry. In this way, follow the steps above to add each of the above layers. Then in the Artwork control form window, click Select All to select all layers, and then click Apertures. . Button, a new window EditAperture Wheels appears, click EDIT, click the AUTO > button in the new window, select with rotation, and some Aperture files are automatically generated. Then click O.K. Clicking Creatartwork in Artwork control form produces 13 art files. Go back to the Allegro window and click the Drill tape menu in the NC option under the Manufacture menu to generate a * .tap file. At this point, all 14 light-painted files were produced.

31. How to look at the light drawing file? And how to make the Plane layer light drawing file of Negtive?

Create a new blank layout file, File- > import- > Artwork, and then you can select * .art file in browse and gerber 6 × 00 in Manual. Be careful not to click OK, click Load File. Put a tick before display pad targets when calling Soldermask. When you call the silkscreen layer, you may find that there is no device name flag. This is because when making the light drawing file above, Underined line width does not define the width, and when making the wrapper library, the Ref marked in the silk_ screen layer does not define the width, so it will not be displayed when called. In addition, if you want to make Negtive light drawing file. When making a light drawing file, the Plot mode of the Gnd and Vcc layers is selected as Negative.

After reading this, the article "what are the common problems in Cadence layout and routing" has been introduced. If you want to master the knowledge points of this article, you still need to practice and use it yourself. If you want to know more about related articles, welcome to follow the industry information channel.

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