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This article mainly explains "what is the logic function of d flip-flop". Interested friends may wish to take a look. The method introduced in this paper is simple, fast and practical. Next let the editor to take you to learn "what is the logic function of d flip-flop"?

The logic function of D flip-flop is that Qn+1=D; is an information storage device with memory function and two stable states. it is not only the most basic logic unit of many kinds of sequential circuits, but also an important unit circuit in digital logic circuits.

The operating environment of this tutorial: windows7 system, Dell G3 computer.

D flip-flop logic function: Qn+1=D.

D flip-flop is an information storage device with memory function and two stable states. it is not only the most basic logic unit of a variety of sequential circuits, but also an important unit circuit in digital logic circuits.

It is widely used in digital systems and computers. Flip-flop has two stable states, namely "0" and "1". Under the action of certain external signals, flip-flops can be reversed from one stable state to another.

Flip-flops are flip-flops composed of integrated flip-flops and gate circuits. There are two trigger modes: level trigger and edge trigger, the former can be triggered when CP (clock pulse) = 1, and the latter can be triggered at the front of CP (positive hopping 0 → 1).

The secondary state of D flip-flop depends on the state of D side before trigger, that is, secondary state = D. Therefore, it has two functions of setting 0 and 1.

For the edge D flip-flop, because the circuit can maintain blocking during the CP=1, the change of the data state of the D side during the CP=1 will not affect the output state of the flip-flop.

D flip-flop is widely used in digital signal storage, shift storage, frequency division and waveform generator and so on.

Extended data

D flip-flop consists of 4 and-no gates, of which G1 and G2 constitute the basic RS flip-flop. When the master-slave trigger triggered by the level is working, the input signal must be added before the positive jump edge. If an interference signal occurs at the input during the high level of the CP, it is possible to cause the state of the trigger to go wrong. The edge trigger allows the input signal to be added immediately before the CP trigger edge arrives.

In this way, the time of interference on the input side is greatly shortened, and the possibility of interference is reduced. Edge D flip-flop is also called maintain-block edge D flip-flop. Edge D flip-flops can be made up of two D flip-flops in series, but the CP of the first D flip-flop needs to be reversed by a non-gate.

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