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This article is to share with you about how to use the PHY register, the editor thinks it is very practical, so I share it with you to learn. I hope you can get something after reading this article.

When STM32 only has network peripherals, it can not communicate on the network, because STM32 only provides SMI interface, MII interface and RMII interface. We also need external network chips, referred to as PHY chips, to communicate with. I am familiar with the PHY models are: RTL8201F,RTL8201E,RTL8201G,DP83848,YT8512C, etc., originally planned to explain RTL8201F, but the content is too much, first take out the PHY register to talk about.

Why doesn't STM32 integrate PHY?

PHY (PortPhysical Layer), which can be called port physical layer in Chinese.

1. The PHY chip is an analog chip, which needs to convert the differential signal of the network line into a digital signal. If integrated, the chip area will increase. If the power consumption is reduced, the chip manufacturing process will be higher, which will directly increase the chip cost.

2. Not all STM32 users need to use the network, and integrating PHY will increase the cost.

Therefore, the fact that STM32 does not integrate PHY is not a technical problem, but the result of various considerations.

Isn't there an integrated MCU for PHY?

Yes, LM3S8962 of TI.

Let's go back to PHY registers. There are three types of external PHY chip registers.

Basic: base register

Extended: extension register

Vendor-spcififc: manufacturer's special register

The following is described in version 2012 of the 802.3 protocol.

Different manuals have different instructions for the basic register. as illustrated in the figure 802.3-2012, the basic registers are the controller register (register 0) and the status register (register 1), and the CNOOC extended status register (register 15) in the GMII (Gigabit Network) interface.

This paper mainly explains the basic registers of PHY according to the 802.3-2012 protocol, not according to a specific chip.

Register 0 and register 1 are located in the protocol document as shown below

The 802.3-2012 protocol mentioned above can be downloaded from the official website of ieee.

Https://standards.ieee.org/

Or download it through Baidu online disk.

Link: https://pan.baidu.com/s/1Nr_KHse32zysBKZ0btPceg

Extraction code: xhin

01. Control register (register 0)

Register 0 is the PHY control register, and the main working state of PHY can be set through ControlRegister.

Bit15 Rset

A bit15 of 1 means that the PHY is reset. Bit15 controls the PHY reset function, and writes 1 in this position to realize the reset operation of PHY. After the reset, the other controls and status registers of the port PHY will be restored to the default value, each PHY reset should be completed within 0.5s, the Bit15 should be kept at 1 during the reset process, and the bit should be cleared automatically after the reset is completed. Generally, when you want to change the working mode of the port (such as rate, duplex, flow control or negotiation information, etc.), after setting the registers of the corresponding location, you need to reset the PHY through the Reset bit to make the configuration effective.

Before the reset process is completed, the PHY is not required to accept the write transaction to the control register, and before the reset process is completed, the write operation to the bits in the control register except bit15 may be invalid.

Bit14 Loopback

Loopback is a function commonly used in debugging and troubleshooting. After Bit14 is set to 1, the connection between PHY and external MDI will be logically disconnected, and the data sent from MAC through MII/GMII (or other MAC/PHY interfaces) will not be sent to MDI, but on the MII/GMII receiving channel that is looped back to this port within the PHY (usually in PCS).

Through the Loopback function, you can check whether the MII/GMII and PHY interface part is working properly, and it can be used for fault location if the port is not connected. It should be noted that in many cases, the port may be Linkdown after PHY sets Loopback, and MAC cannot send frames to this port. In this case, you need to set port ForceLink up to use the Loopback feature.

Bit13 Speed Selection (LSB)

Bit13 and Bit6 jointly realize the rate control function of the port. The specific corresponding relationship is shown in the following figure.

It should be noted that SpeedSelection works only if autonegotiation is turned off. If autonegotiation is set to Enable, this setting does not work.

Moreover, to modify the settings of SpeedSelection, it is often necessary to reset the port before the configuration can take effect. Therefore, when setting this location, you need to check the setting of autonegotiation and reset the port through Bit15.

Bit12 Auto-Negotiation Enable

Automatic negotiation (AN) switch. A setting of 1 turns on the AN function, and the mode of operation of the port is determined by autonegotiation with the connected peer. If set to 0, the autonegotiation function is turned off, and the working mode of the port is determined by the configuration of the corresponding location of the ControlRegister. It must be noted that for the 1000BASE-T interface, autonegotiation must be turned on.

Bit11 Power Down

Port working switch: setting to 1 will make the port enter PowerDown (low power state) mode. Normally, PHY will not send data to MII and MDI in PowerDown mode. PowerDown mode is generally used in the software shutdown port, it should be noted that the port is restored from PowerDown mode, the port needs to be reset to ensure a reliable port connection.

Bit10 Isolate

Isolation status switch: changing position 1 will result in electrical isolation between the PHY and MII interfaces, with MII pins in a high resistance state except for signals from the MDC/MDIO interface. IEEE802.3 does not regulate the state of the MDI interface during Isolate, and the MDI side may still be running normally. Isolate is not used in practical application. And, it is worth noting that, since the mainstream MAC interfaces of many 100-megabit PHY chips are SMII/S3MII,8 ports are interrelated, setting Isolate on one port may affect the normal use of other ports, so be careful not to change the state of bit10 at will in use.

Bit9 Restart Auto-Negotiation

Restart the autonegotiation switch: Bit9 setting 1 will restart the autonegotiation process for the port, of course, provided that Auto-NegotiationEnable is enabled. Generally, after modifying the autonegotiation capability information of the port, Bit9 setting 1 is used to restart autonegotiation to make the port establish link according to the new configuration.

Bit8 Duplex Mode

Duplex mode setting: Bit8 sets port 1 to full-duplex, and 0 sets port to half-duplex. Like the setting of SpeedSelection, the setting of DuplexMode only works when auto-negotiation is turned off. If auto-negotiation is set to Enable, this setting does not work. The duplex mode of the port is determined according to AN results. Changes to the configuration of the DuplexMode also need to reset the port to take effect.

Bit7 Collision Test

Collision signal (COL) test switch: when you need to test the COL signal, you can set 1 through Bit7, then PHY will output a COL pulse for testing. In the actual test operation, the port can also be configured as a half-duplex state, and the COL signal can be tested by sending frame conflicts, so this configuration is of little practical value.

Bit6 Speed Selection (MSB)

Combine with Bit13 to realize the rate control function of the port.

Bit5 Unidirectional enable

When the 12th bit is 1 or the 8th bit is 0, the bit is ignored.

When the 12th position is 0 and the 8th position is 1:

1: enable transmission from the MII interface, regardless of whether the PHY determines that a valid link is established

0: enable transmission from the MII interface only if PHY determines that a valid link has been established

Bits 4:0 reserved

Reserved bits, which should be written to zero and ignored when reading; however, PHY should return the value zero in these bits.

02. Status register (register 1)

Register 1 is the PHY status register, which mainly contains the status information of PHY.

Bit15 100BASE-T4

The ability of PHY to perform link transmission and reception using the 100BASE-T4 signaling specification. 1: capable; 0: incompetent.

Bit14 100BASE-X Full Duplex

PHY uses the 100BASE-X signaling specification to perform full-duplex link transmission and reception. 1: capable; 0: incompetent.

Bit13 100BASE-X Half Duplex

PHY uses the 100BASE-X signaling specification to perform half-duplex link transmission and reception. 1: capable; 0: incompetent.

Bit12 10Mb/s Full Duplex

PHY has the ability to perform full-duplex link transmission and reception at the speed of 10Mb/s. 1: capable; 0: incompetent.

Bit11 10Mb/s Half Duplex

PHY has the ability to perform half-duplex link transmission and reception at the speed of 10Mb/s. 1: capable; 0: incompetent.

Bit10 100BASE-T2 Full Duplex

PHY has the ability to perform full-duplex link transmission and reception using the 100BASE-T2 signaling specification. 1: capable; 0: incompetent.

Bit9 100BASE-T2 Half Duplex

PHY has the ability to perform half-duplex link transmission and reception using the 100BASE-T2 signaling specification. 1: capable; 0: incompetent.

Bit8 Externded Status

1: enable register 15

0: do not enable register 15

Bit7 Unidirectional ability

1:PHY has the ability to encode and transmit data from PHY through the MII interface, regardless of whether or not PHY has determined that a valid link has been established.

0: enable transmission from the MII interface only if PHY determines that a valid link has been established

Bit6 MF Preamble Suppression

1:PHY can accept management frames, regardless of whether they are preceded by a preamble mode or not.

0:PHY cannot accept management frames unless they are preceded by a preamble mode.

Preamble mode.

It is described in the official document 22.2.4.5.2. You can check it out for yourself.

As a matter of fact, we have also explained this preamble before. In the article "SMI Interface of STM32 Network", it is recommended that students who have not read this article read it.

Bit5 Auto-Negotiation Complete

AN completion status indication bit: Bit5 indicates whether the port AN process is completed or not. In the case of ANEnable, Bit5=1 indicates that the autonegotiation process has ended successfully, and other registers related to the Link status of PHY are correct and reliable. If the AN process does not complete, the status information may be incorrect. When debugging and handling abnormal faults, we can judge whether the AN is successful by the status of the bit register, so as to further check whether the settings related to AN are correct, or whether the AN function of the chip is normal.

Bit4 Remote Fault

Remote error indication bit: Bit4=1 stands for LinkPartner error, as for the specific type of error and error detection mechanism are not defined in the specification, PHY manufacturers are free to play, generally manufacturers will indicate more detailed error types in other registers (Register16-31 defined by the manufacturer). RemoteFault is an important indicator in port-related fault verification, which can help locate the cause of the fault by interconnecting the RemoteFault information of both parties (which may need to be added with other specific error indications).

Bit3 Auto-Negotiation Ability

1:PHY enables autonegotiation

0:PHY does not enable automatic negotiation

Bit2 Link Status

Link status indicator bit: Bit2=1 represents port Linkup,0 and represents port Linkdown. In practical applications, Bit2 is generally used to judge the status of the port. Moreover, a typical MAC chip determines the Link status of a port by polling this register value of PHY (this process may have different names, such as BCM is called LinkScan and Marvell is called PHYPolling. As mentioned earlier, in the case of ANEnable, the information of LinkStatus is correct and reliable only if the Auto-NegotiationComplete indicates that it has been completed, otherwise errors may occur.

Bit1 Jabber Detect

1: jitter (prick) state detected

0: no jitter (prick) state detected

Bit0 Extended Capability

1:PHY provides an extended feature set that can be accessed through an extended register set.

0: no extension register is provided.

03, register 15

Register 15 main mode gigabit mode, PHY status.

As shown in the figure above, register 15 mainly describes the status of PHY in gigabit mode, which is similar to the relevant bits of register 1.

Bit15 1000BASE-X Full Duplex

PHY uses the 1000BASE-X signaling specification to perform full-duplex link transmission and reception. 1: capable; 0: incompetent.

Bit14 1000BASE-X Half Duplex

PHY uses the 100B0ASE-X signaling specification to perform half-duplex link transmission and reception. 1: capable; 0: incompetent.

Bit13 1000BASE-T Full Duplex

PHY has the ability to perform full-duplex link transmission and reception using the 1000BASE-T signaling specification. 1: capable; 0: incompetent.

Bit12 1000BASE-T Half Duplex

PHY has the ability to perform half-duplex link transmission and reception using the 1000BASE-T signaling specification. 1: capable; 0: incompetent.

Bits 11:0 reserved

The bit is reserved and ignored when reading.

04. Other registers

In addition to the basic registers, the 802.3-2012 protocol also mentions other registers, which are briefly explained here and do not focus on.

Registers 2, 3: chip ID registers

Registers 2 and 3 are PHYID registers, respectively. It is known from the kernel code that register 2 (PHYID1) is high 16 bits and register 3 (PHYID2) is low 16 bits. As the logo of PHY chips, they are generally considered to be of little use. In the past, there have been different boards with the same main CPU with different PHY combinations, using the same kernel, here we can use PHYID to make a difference.

Register 4: auto-negotiate notification register

The register preserves the characteristics and capabilities of PHY itself. For example, PHY supports flow control, 100 megabit full duplex / half duplex, 10 megabit full duplex / half duplex, etc.

Advertise on the MDI via FLP when set to autonegotiation enabled. If it is not enabled, the configuration of this register is invalid.

Register 5: auto-negotiate peer capability notification register

This register is similar to register 4 in that it represents the characteristics and capabilities of the peer (switch or PC). It should also be noted that the register information is valid only if autonegotiation is enabled. Because this register represents the state of the opposite end, the value of the register is generally designed to be read-only, but some chips, such as dm9000's flow control bit 5.10FCS, are readable and writable.

The register is mainly used to understand the situation of the opposite end, when there is a problem, you can know the information of the other side, so as to roughly locate the range. Instead of blindly looking for your own reasons. In case there is a failure of the switch at the opposite end, this register is strong on-site evidence.

The above is how to use the PHY register. The editor believes that there are some knowledge points that we may see or use in our daily work. I hope you can learn more from this article. For more details, please follow the industry information channel.

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