Shulou(Shulou.com)06/02 Report--

This article mainly introduces "the simple implementation of clock switching of AND- OR multiplexer logic". In daily operation, it is believed that many people have doubts about the simple implementation of clock switching of AND- OR multiplexer logic. The editor consulted all kinds of data and sorted out simple and useful operation methods. I hope it will be helpful to answer the question of "simple implementation of clock switching of AND- OR multiplexer logic". Next, please follow the editor to study!

As more and more clocks are used in today's chips, clocks usually need to be switched while the chip is running.

We can reuse two clock sources of different frequencies in the chip, and the selection signal of the multiplexer is controlled by the internal logic.

The two clock frequencies reused can be completely independent or multiples of each other. In either case, it is possible to generate burrs during clock switching. The burr on the clock can cause a failure of the entire system function, because it may be regarded as the edge of the clock by some registers and ignored by others.

The figure above shows a simple implementation of clock switching using AND- OR multiplexer logic.

The multiplexer has a control signal called SELECT

When set to "SELECT = 1'b0", it propagates CLK0 to the output

CLK1 is propagated to the output when set to "SELECT = 1'b1". Burrs may occur when the select value changes.

The timing diagram in the above figure shows how the output OUT CLOCK produces burrs when the SELECT control signal changes.

The above figure shows a solution to prevent burrs from clock switching. A D trigger triggered by a negative edge is inserted into the selection path of each clock source. After other clocks are not enabled, the selection control signal is registered on the falling edge of the clock, which can prevent the output signal from burring.

Registering the selection signal at the falling edge of the clock ensures that the output does not change when the clock is at high power level.

In the above timing diagram, the SELECT signal changes from 0 to 1, stopping the CLK0 propagation to the output at the falling edge of the CLK0, and then starting the CLK1 propagation to the output at the subsequent falling edge of the CLK1.

There are three timing paths in the circuit that need special consideration-the SELECT control signal to the two negative edges trigger, the DFF0 output to the input of DFF1, and the output of DFF1 to the input of DFF0.

If the signal on any of these three paths is close to the edge of the trigger clock, the output of the register is likely to become metastable.

As shown in the above figure, by adding an extra positive edge trigger to each clock source, the data is stabilized to prevent metastable propagation.

The clock switching technology of the above glitch free avoids burrs during clock switching with very little overhead. These techniques can be extended to more than two clock switches.

For multiple clock switching, the selection signal of each clock will receive feedback from all other clock sources.

At this point, the study of "simple implementation of clock switching of AND- OR multiplexer logic" is over. I hope to be able to solve your doubts. The collocation of theory and practice can better help you learn, go and try it! If you want to continue to learn more related knowledge, please continue to follow the website, the editor will continue to work hard to bring you more practical articles!

Welcome to subscribe "Shulou Technology Information " to get latest news, interesting things and hot topics in the IT industry, and controls the hottest and latest Internet news, technology news and IT industry trends.