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Most people don't understand the knowledge points of this article "How to automatically identify memory size in Android", so Xiaobian summarizes the following contents for everyone. The contents are detailed, the steps are clear, and they have certain reference value. I hope everyone can gain something after reading this article. Let's take a look at this article "How to automatically identify memory size in Android".

1. MINI6410 memory hardware structure and addressing relationship

Memory hardware structure on MINI6410:

For the MINI6410 design, two pin-compatible DDR memory chips were used to achieve 128MB of memory and 256MB of memory sharing a single PCB.

The 128MB memory uses two K4X51163PG (32 MB x 16bit) chips, forming a 32 MB x 32bit (128MB) memory. The 256MB memory uses two K4X1G163 PEs (64 MB x 16bit), forming a 64 MB x 32bit (256MB) memory. The difference between the two chips is that the F7 of the K4X51163PG is the NC pin, while the F7 of the K4X1G163PE is the A13 pin. This F7 pin is disconnected in the 128MB version of the MINI6410, while in the 256MB version it is connected to the Xm1ADDR13 of the S3C6410 via a 0 ohm resistor.

Those of you who read the data sheets for these two memory chips and the S3C6410 (DRAM controller) must know that this connection forms an addressing relationship like this:

128MB Memory Version: Xm1ADDR[15:14](bank): Xm1ADDR[12 :0](row address): Xm1ADDR[9:0](column address). A total of 25 address lines address exactly 32 megabytes of space. 256MB Memory Version: Xm1ADDR[15:14](bank): Xm1ADDR[13 :0](row address): Xm1ADDR[9:0](column address). A total of 26 address lines address exactly 64 megabytes of space. These two connections and chip configurations are matched by modifying the parameters of two registers in the DRAM controller of the S3C6410.

2. Location of memory adaptive code in U-boot

Having prepared for the above two knowledge, let's look at where in u-boot we should recognize and adapt to different memory sizes.

First we may need to reconfigure the memory controller of the S3C6410 after identifying the memory size. As a result, the code cannot run in DDR. Because once the memory controller is reconfigured, it will inevitably cause the memory to be temporarily unavailable. If the code is in DDR, the CPU may not be able to get the next code. So this code should be placed before u-boot implements self-copying into memory. In fact, the *** place is in the code segment that initializes the memory controller in the SPL section of u-boot.

The code is in arch/arm/cpu/arm1176/s3c64xx/cpu_init.S

This file is assembly code, where the function mem_ctrl_asm_init is called by lowlevel_init "bl mem_ctrl_asm_init" in start.S--->/board/samsung/mini6410/lowlevel_init.S. The code in the mem_ctrl_asm_init function initializes the DRAM controller of the S3C6410 and also initializes the external DDR memory, so memory identification and adaptation code should be placed after these initializations. First identify the size of the memory, if the memory size does not match the original DRAM controller configuration, modify the DRAM controller configuration.

3. Identification of memory size

In the case of the MINI6410, we only need to identify whether the memory is 128MB or 256MB. Since these two memory sizes are related to the parameters of the two registers of the DRAM controller, we must first assume our memory size, and then prove it by reading and writing. If our assumption is proved to be wrong, then modify the parameters of the registers.

My ported U-boot code assumes 256MB of memory and configures the DRAM controller for 256MB of memory. If 128MB of memory is connected, then there is an interesting phenomenon:

Since Xm1ADDR [13 ] is not connected, the *** 8M ×32bit (32MB) and the second 8M ×32bit (32MB) of DDR memory are mirror images, the third 8M ×32bit (32MB) and the fourth 8M ×32bit (32MB) are mirror images, and so on. There are four such mirror relationships, totaling 256MB. If the connection is 256MB of memory, there will be no such phenomenon. So, once we prove that this phenomenon exists, we prove that we are actually connecting 128MB of memory, and then reconfigure the DRAM controller to 128MB of memory parameters and we are done.

Therefore, in the U-boot code I transplanted, I first wrote a 32-bit test data to a certain position (such as 0x0 address) of *** 8M×32bit (32MB), and then went to the corresponding offset position of the second 8M×32bit (32MB) to read. If the data is consistent, the mirror relationship can be proved. But it's not safe. What if it happens (in the case of connecting 256MB of memory) that the corresponding position of the second 8M×32bit (32MB) is this data itself? It doesn't matter, we go to the second 8M×32bit (32MB) to write another test data at the same position, and then go to the *** 8M×32bit (32MB) position (that is, the first write position) to read the data. If the data is consistent, it can completely prove the mirror relationship. Run this test twice to see if you want to reconfigure the DRAM controller parameters

However, we cannot assume that the memory is 128MB and configure the DRAM controller for 128MB of memory parameters first. If 256MB of RAM is connected, nothing special can be detected. Through the above addressing relationship, if the connection is 256MB of memory, only the second, fourth, sixth, and eighth (assuming Xm1ADDR[13 ] is always 0) 8M ×32 bits (32MB) are inaccessible (can be said to be memory holes), which cannot be proved by reading and writing. (inferred by addressing relationships, not experimentally proven)

4. Reconfiguration of memory controller

If the above steps test out the existence of the mirror, we must reconfigure the values of the two registers, but how to reconfigure, this Samsung data manual is not said, I found through testing can reconfigure the DRAM controller by the following steps:

1. Set DRAM controller to Paused state;

2. Test P1MEMSTAT until Paused status is confirmed;

3. Set DRAM controller to Config state;

4. Test P1MEMSTAT until Config status is confirmed;

5. Modify registers that need to be reconfigured

6. Set the DRAM controller to the Go state;

7. Test P1MEMSTAT until ready status is confirmed;

The above is the content of this article about "how to automatically identify memory size in Android". I believe everyone has a certain understanding. I hope the content shared by Xiaobian will help everyone. If you want to know more relevant knowledge, please pay attention to the industry information channel.

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