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This article mainly introduces "how to create basic clock cycle constraints in the server". In daily operation, I believe that many people have doubts about how to create basic clock cycle constraints in the server. I have consulted all kinds of materials and sorted out simple and easy-to-use operation methods. I hope it will be helpful for you to answer the doubts about "how to create basic clock cycle constraints in the server". Next, please follow the editor to study!

Xilinx recommends that temporal and physical constraints be written separately. (but there must be one as target)

Temporal constraints are used for synthesis and implementation, and physical constraints are used for implementation.

1 clock cycle

2 duty cycle

3 phase

Waveform= {rising edge time, falling edge time}

1.Primary clock

First of all, it is determined that Primary clock refers to the crystal oscillator clock provided on the board, which is usually connected to the cc pin of the FPGA, and the other case is the gigabit transceiver. All subsequent timing constraints are derived from Primary clock.

Primary clock refers to the clock on the pin. Create a code with a clock cycle of 10ns.

Create_clock-period 10 [get_ports sysclk] / / assigned to the sysclk pin

two。 Generate clock clock

2.1 user-defined generation clock command: create_generated_clock

2.2 automatically inferred clocks such as MMCM or PLL or BUFR (frequency division generation clock)

These do not need to be constrained, only the primary clock needs to be constrained.

First create a primary clock:

Create_clock-name clkin-period 10 [get_ports clkin]

Then specify the generate clock in two ways:

The first way: create_generated_clock-name clkdiv2-source [get_ports clkin]\-divide_by 2 [get_pins rega/q]

The second way: create_generated_clock-name clkdiv2-source [get_pins REGA/C]\-divide_by 2 [get_pins rega/q]

The third way: create_generated_clock-name clkdiv2-source [get_pins REGA/C]\

-edges {1 35} [get_pins rega/q]

The clock generated by MMCM can be renamed:

Create_generated_clock-name clk_rx [get_pins clk_gen_i0/clk_core_i0/inst\

/ mmcm_adv_inst/clkout0]

3. Clock grouping

3.1 synchronize the clock

3.2 Asynchronous clock

3.3 non-expandable clock

At this point, the study on "how to create basic clock cycle constraints in the server" is over. I hope to be able to solve your doubts. The collocation of theory and practice can better help you learn, go and try it! If you want to continue to learn more related knowledge, please continue to follow the website, the editor will continue to work hard to bring you more practical articles!

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