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EMC in the PCB design should pay attention to which problems, many novices are not very clear, in order to help you solve this problem, the following editor will explain in detail for you, people with this need can come to learn, I hope you can get something.

The EMC problem in PCB design mainly focuses on the following aspects (focusing on wiring): layout

Laminated structure: strictly control the characteristic impedance within the standard range to ensure that the distance from the alignment to the reference layer is less than the distance to other layers, which is the premise of board-level EMC design. The reference plane is as complete as possible, and the high-speed signal had better refer to GND.

High-speed and low-speed circuits, digital and analog circuits, and IO circuits all have their own areas as far as possible to avoid overlap.

Divide regions according to the way of functional modules, and try to avoid regional overlap.

Layout requirements:

1. The high frequency signal is separated from the input and output signal.

2, clock chip / turn-on MOS tube away from IO connector.

3. The relevant functional modules are placed close to the connector.

4, the distance between the alignment layer and the reference layer is less than the distance to other layers.

5. The pressure plate structure must ensure that the characteristic impedance of the wiring is within the range of the specification.

Cabling

One of the guiding principles of wiring is that the current must form a complete circuit, so we have to artificially set a path for it to follow the path we want, and to make the loop as small as possible.

The forward current path is the line of our actual Lay, so what about the reverse reflux path?

The ground wire current of high frequency signal always chooses the path with the lowest impedance Z (not resistance R). This path is not the straight path from the terminal to the source (minimum resistance R), but the path mirrored by the alignment on the reference layer (minimum impedance Z). That is, the path projected by the line on its adjacent reference plane. What we need to do is to ensure that the path is continuous, so that the loop area is the smallest and the electromagnetic radiation generated is the minimum.

For the signal loop to be truly continuous, not only the wiring part, but also the source and terminal, and even the internal IC should be taken into account.

Reflux of the signal:

The reflux current of the high-speed signal is not completely under the signal line, but is distributed directly below and on both sides according to a certain current density, and the current density directly below it is the largest, decreasing to both sides. If the signal is too close to the edge of the board, some of the reflux current will return to the source in the form of space radiation, resulting in electromagnetic radiation.

Cabling rules:

1. The high-speed signal refers to the complete reference plane and must not cross the island.

2, at least 3W apart from the side of the island (power island, ground island)

3. For the IO port with split GND_Chassis, each IO port should have the capacitance from GND to GND_Chassis.

Those conditions can lead to circuit discontinuity: changing layers, crossing islands, and incomplete reference layers.

The change of the layer can be divided into several cases: the signal changes the layer but the reference plane does not change, the reference plane changes but its attribute remains the same, the reference plane changes and its attribute also changes.

Cross-island: the copper skin of the alignment is not continuous in the projection area of the reference plane.

Cabling rules:

Directly change layers and add ground nails in two strata

The maximum distance between ground nail or through-hole capacitance and layer-changing through-hole should not exceed 3W.

The replacement hole should be in the reference plane, not outside the reference plane or at the edge.

As a prerequisite, when faced with the choice of passing holes or crossing islands, we should choose through holes.

Clock signals are not allowed to cross the island.

The distance between clock signal, high-speed signal and other signal lines is at least 3W

Clock signal, high-speed signal wiring must not pass through high-speed, high-power and other devices, and cannot pass under IO connectors and slots

Clock chips, clock Buffer and other high-speed devices cannot pass through other signals.

Clock signal force IO connector side board above 300mil, other positions above board edge 200mil

When there is self-winding (such as serpentine winding), the wire spacing is at least 5W.

The alignment shall not run in parallel with the IO line, and the distance between the lines shall be at least 5W

The clock line should be in the inner layer as much as possible.

The difference ensures that the distance between the difference pairs is above 20mil.

According to the signal flow direction, the primary and secondary signal wiring of the filter and the transformer should not overlap, and the serpentine winding also has this requirement.

The distance between the RGB model and other signal lines and island edge (power island, ground island) is at least 5W.

The IO circuit looks from the connector to the advanced protective device, and then the filter circuit, all of which need to be close to the connector.

When the high-speed signal passes through the filter device and the protective device, it should pass in turn according to the signal flow direction, and the branch line should not appear. For example, the RGB signal should pass through the PIN foot of the protective IC, and can not lead the branch line to the protective IC alone.

The clock signal line can be switched in the reference plane, but the switching times should be controlled within 3 times as much as possible.

The source matching resistance of the clock signal should be placed near the clock output pin.

The impedance matching of RGB signal should be guided by the chip design.

Use obtuse angles for line turns, not right angles and acute angles.

High-speed signal and clock signal can not be terminated, especially in the reservation scheme, there are 0 ohmic resistors at both ends of the signal.

Crosstalk:

If the distance between the signal lines is too small, due to the influence of the distributed capacitance between the lines, the high-frequency signals between the signal lines will crosstalk each other, affecting the signal quality, resulting in EMC problems.

In particular, the IO signal, if crosstalk to high-frequency noise, it is easy to cause serious radiation through the peripheral lead.

The distributed capacitance between signal lines is related to the distance between lines, the length of parallel lines, the positive area and other factors, so in order to reduce the crosstalk between signal lines, the distance between lines should be increased and the length of parallel lines should be reduced. Parallel alignment should be avoided in the adjacent wiring layer, because its distributed capacitance is also very large, which requires vertical alignment in principle.

The degree of crosstalk is not only related to the distributed capacitance, but also related to the frequency and amplitude of the signal, which is why high-frequency signals are more prone to crosstalk.

Impedance matching

For the high-speed signal, its routing path requires impedance matching. When the impedance is mismatched, it will produce reflection at the impedance discontinuous point, which will affect the signal quality and lead to EMC problems.

If a set of signals from the source-wire-terminal such a path, the source impedance = the characteristic impedance of the wiring = the terminal impedance, in this ideal case there will be no reflection. It can be understood that the greater the impedance change, the greater the signal reflection, and the more serious the EMC problem will be. The branch alignment, terminal no-load and other situations are very serious impedance mismatch.

Power decoupling

Between functional modules (between chips), power and ground time are shared, and the noise generated by the module is easily coupled through these two common paths, resulting in serious EMC problems.

The ground tends to have a large area and a separate layer, so it is relatively clean (very little noise).

The power supply needs to be decoupled to ensure that the circuit will not affect other circuits when it works.

In order to ensure the filtering effect of the capacitor, the impedance Z from the capacitor to the power supply or ground must be as small as possible.

For the wired power supply, make sure that each power supply PIN pin has a 0.1uF capacitor, and the wiring should be thickened.

For the BGA chip, there is at least one capacitance of 0.1uF and 0.01uF distributed on each of the four corners.

The filter circuit of the power supply is placed according to the schematic diagram, and the capacitance and magnetic beads are placed as close to the chip as possible.

The filter capacitor is punched directly into the formation as far as possible, and if the alignment must be used, the alignment should be short and thick.

A through hole to the power supply or ground allows up to two capacitors to be used.

Signal filtering and protection

IO signals generally need to be connected to peripherals, and peripherals generally have longer connections. If IO signals (including power supply and ground) have high-frequency noise, it is easy to generate large radiation to space through peripheral connections. Therefore, IO signals need to be filtered.

In order to avoid the secondary pollution of the filtered signal in the board, the filter circuit should be placed close to the port.

External equipment is also easy to introduce external interference, even destructive interference, so it is necessary to use protective devices and put them in front of the filter circuit to prevent destructive interference from invalidating the filter circuit.

Safety regulation

Safety regulations: between lines with electrical isolation requirements, they must be able to withstand the specified voltage without insulation damage.

Setting rules: copper (via trace shape pad) belonging to different lines should ensure a certain airgap distance to withstand the specified voltage.

Same layer: the outer insulation medium is air, and the breakdown voltage strength is 3KV/mm. The inner insulating medium is FR4.

Different layers: insulating medium is FR4, breakdown electric field strength is 15KV/mm. Attention should be paid to the non-uniformity of electric field distribution.

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