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01. PWM introduction

PWM definition: pulse width modulation (PulseWidthModulation,PWM) is referred to as pulse width modulation. Generally speaking, PWM is a method to digitally encode the analog signal level. Through the use of high-resolution counters, the duty cycle of the square wave is modulated to encode the level of a specific analog signal. The PWM signal is still digital because at any given time, the full amplitude DC power supply is either completely available (ON) or completely absent (OFF). The voltage or current source is added to the analog load as an ON or OFF repetitive pulse sequence. When on, that is, when the DC power supply is added to the load, and when it is cut off, that is, when the power supply is disconnected. Any analog value can be encoded using PWM as long as the bandwidth is sufficient.

Duty cycle definition: duty cycle is the time that the high level takes up the entire cycle, as shown in the following figure:

The first PWM wave, the period is 10ms, the high level time is 4ms, so the duty cycle is 40%, similarly, the second PWM wave is 60%, and the third is 80%.

The frequency of PWM: the reciprocal of the whole cycle of the frequency of PWM, so the period of PWM in the figure above is 1Universe 0.01, that is, 100HZ. Changing the frequency of the PWM is achieved by changing the entire cycle. Therefore, PWM waves with arbitrary frequency and duty cycle can be realized by changing the total time of high and low level and the ratio of high level to total cycle.

The uses and advantages of PWM: motor speed regulation, power modulation, PID regulation, communication, etc., simple configuration, strong anti-interference ability, from the processor to the controlled system signals are in digital form, no need for digital-to-analog conversion. And keeping the signal in digital form can minimize the noise impact, and the noise can have an impact on the digital signal only when the noise is strong enough to change logic 1 to logic 0 or logic 0 to logic 1, which is the main reason why PWM is used in communication.

02. Pin reuse of STM32

STM32 does not have a dedicated PWM pin, so it uses the reuse mode of the IO port. First confirm the output pin of the PWM function, using timer 9. As you can see from the block diagram below, timer9 has only two output channels, so timer9 can only output two PWM.

In the Alternatefunction mapping picture in the STM32F207 data manual, the two channels of timer9 can be reused as PA2,PA3,PE5 and PE6, respectively.

03. STM32 output PWM principle

The ① section in the following figure is explained in the "STM32 basic timer explanation", and the shadow register is also described in the "STM32 shadow register". I will not repeat it below. This article will focus on the ② part, capture / comparison channel explanation, in which the PWM of STM32 is implemented using the comparison channel.

Pulse Width Modulation mode allows you to generate a signal with afrequency determined by the value of the TIMx_ARR register and a dutycycle determined by the value of the TIMx_CCRx register .

Excerpt from STM32F207 Reference manual manual

The pulse width modulation mode can generate a signal whose frequency is determined by the TIMx_ARR register value and its duty cycle is determined by the TIMx_CCRx register value.

As you can see from the following figure, an action occurs when the CCR register is the same as the CNT counter (changing the GPIO level corresponding to the channel). Because when CNT overflows, the overload value is determined by the TIMx_ARR register value. So the TIMx_ARR register value determines the period, while the TIMx_CCRx register value determines how long the CNT overflow will take place (changing the GPIO level corresponding to the channel), that is, determining the duty cycle.

Take the upward count as an example, the overload value is ARR and the comparison value is CRRx

As can be seen in the above picture:

0-t1 section, timer counter TIMx_ CNT value is less than CCRx value, output low level.

T1-t2 section, timer counter TIMx_CNT value is greater than CCRx value, output high level.

When the TIMx_ CNT value reaches ARR, the timer overflows and counts up again. Cycle this process until this PWM cycle is complete.

The picture above illustrates more vividly.

The signal frequency is determined by the TIMx_ARR register value.

The duty cycle is determined by the TIMx_CCRx register value.

The process of STM32 outputting PWM:

1. First configure GPIO and timer. Refer to the code for details. Timer configuration reference "STM32 basic timer details".

2. Capture / compare channels enable comparison channels.

As you can see in the image above, the name of the ① register is: Capture/Compare1register. You can choose to input capture from ②, or you can choose to output from ③, which is the PWM output function we need. Choose the capture channel or the comparison channel. No specific description is found in the block diagram, but the control bit is enabled in the TIMx_CCMR1 register CC1S [1:0].

3. After enabling the output, it is time to configure the PWM output

OC1M [2:0] bit of the ① TIMx_CCMR1 register, which sets the output mode controller

110:PWM mode 1 0111 PWM mode 2.

The ② counter value TIMx_CNT is compared with the channel 1 capture comparison register CCR1, and the effective level and invalid level are output by comparing the results.

OC1REF=0 invalid level, OC1REF=1 invalid level.

③ outputs the signal generated by the mode controller. The CC1P bit of the TIMx_CCER register sets the input / capture channel 1 output polarity.

0: high level is effective, 1: low level is effective.

The ④ TIMx_CCER:CC1E bit controls the output enable circuit, from which the signal is output to the corresponding pin.

0: off, 1: on.

First, PWM mode 1 and PWM mode 2 are introduced:

Mode 1

When counting upward, channel 1 is invalid level (OC1REF=0) once TIMx_CNTTIMx_CCR1, otherwise it is effective level (OC1REF=1).

Mode 2

When counting upward, channel 1 is a valid level once TIMx_CNTTIMx_CCR1, otherwise it is invalid.

Channel 1 is valid when TIMx_CNT > TIMx_CCR1, otherwise it is invalid.

The output level of PWM is determined by both TIMx_CCMR1: OC1M bit and TIMx_CCER:CC1P bit.

To sum up:

Mode 1:

CNTCCR is invalid level / / (OC1REF = 0)

Mode 2:

CNTCCR is the effective level / / (OC1REF = 1)

CC1P:

0: high level effective

1: low level effective

04. STM32 output PWM configuration

After analyzing the principle, let's analyze the process of generating PWM by STM32.

1. First, set GPIO to reuse output.

/ * GPIOE clock enable * / RCC_AHB1PeriphClockCmd (RCC_AHB1Periph_GPIOE, ENABLE); / * GPIOE Configuration: TIM9 CH2 (PE6) * / GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5 | GPIO_Pin_6;GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; GPIO_Init (GPIOE, & GPIO_InitStructure) / * Connect TIM9 pins to AF3 * / GPIO_PinAFConfig (GPIOE, GPIO_PinSource5, GPIO_AF_TIM9); GPIO_PinAFConfig (GPIOE, GPIO_PinSource6, GPIO_AF_TIM9)

2. Configure timer to count upward and configure timer frequency

/ * TIM9 clock enable * / RCC_APB2PeriphClockCmd (RCC_APB2Periph_TIM9, ENABLE); / * Compute the prescaler value * / PrescalerValue = (uint16_t) ((SystemCoreClock) / 2000000)-1; / * Time base configuration * / TIM_TimeBaseStructure.TIM_Period = 1000-1 × TIMBASE structure. TIMP é Prescaler = PrescalerValue;TIM_TimeBaseStructure.TIM_ClockDivision = 0 position TIMP (TIM9, & TIM_TimeBaseStructure)

3. Configure PWM output

The above analysis process is troublesome. ST provides a standard peripheral library, and we only need to configure the TIM_OCInitTypeDef structure.

TIM_OCInitTypeDef TIM_OCInitStructure; / * PWM Mode configuration: Channel1 * / TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1;TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;TIM_OCInitStructure.TIM_Pulse = 100-1; TIMP OCInitStructure = TIM_OCPolarity_High; TIM_OC1Init (TIM9, & TIM_OCInitStructure); TIM_OC1PreloadConfig (TIM9, TIM_OCPreload_Enable)

Analysis of TIM_OCInitTypeDef structure

Typedef struct {uint16_t TIM_OCMode; / / PWM Mode 1 or Mode 2 uint16_t TIM_OutputState; / / output enable OR disable uint16_t TIM_OutputNState; / / PWM output does not require uint32_t TIM_Pulse; / / comparison value uint16_t TIM_OCPolarity;// comparison output polarity uint16_t TIM_OCNPolarity; / / PWM output does not require uint16_t TIM_OCIdleState / / PWM output does not require uint16_t TIM_OCNIdleState; / / PWM output does not require} TIM_OCInitTypeDef

TIM_Pulse can be set during initialization and can also be updated again through the following API.

Void TIM_SetCompare1 (TIM_TypeDef* TIMx, uint32_t Compare1)

4. Enable timer

TIM_ARRPreloadConfig (TIM9, ENABLE); / * TIM9 enable counter * / TIM_Cmd (TIM9, ENABLE)

Use timer9 to output the waveform of PWM

Thank you for reading! This is the end of this article on "sample Analysis of STM32 PWM output". I hope the above content can be of some help to you, so that you can learn more knowledge. if you think the article is good, you can share it for more people to see!

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