Shulou(Shulou.com)06/01 Report--

In this issue, Xiaobian will bring you about the architectural difficulties of EMC VMAX. The article is rich in content and analyzed and described from a professional perspective. After reading this article, I hope you can gain something.

Today I want to share with you two questions about VMAX architecture, one is how is the claimed bandwidth of 40K calculated? The other one is, is there a VMAX engine and VNX co-platform?

Let's look at the first question first. The specifications on the VMAX 40K datasheet include the bandwidth of the virtual matrix. How is this bandwidth calculated?

Today, I checked online, there is no accurate statement, but there is a netizen's analysis seems to be more detailed. As you know, VMAX uses Rapid IO switching technology standard interconnects.

The 2009 first-generation VMAX featured an older version of RAPID IO at 3.125Gb, while the 2012 VMAX release featured a newer version of RAPID IO at 6.25Gb bandwidth.

The 40K has eight engines, each engine has two directors, and each Director is a computer system.

The internal architecture of each Director is shown in the figure. This is a schematic based on VMAX Gen 1. No schematics found for VMAX Gen 2.

"Given that the VMAX 40K has twice the number of virtual matrix interfaces and twice the signaling rate, the quoted VM value of 50GB/s can only represent a bidirectional encoding rate of 6.25 Gbaud on 8x4 lanes on RapidIO. "

That is to say, 40K each engine 50GB/s bandwidth how to calculate, that is, before doing 8b/10b encoding, each connection is 6.25Gb, each interface is x4 lanes interface connected to Rapio IO switch, a Director has 4 ports, an engine has two Directors, that is 8 interfaces. Thus, the bandwidth of an engine connected to the switch is 6.25Gb*4*8/8=25GB/s, which is unidirectional, or 50GB/s if bidirectional. So the entire system is 8 engines, so 40K virtual matrix bandwidth is 400GB/s. It turns out that many people speculate that EMC propaganda is so high that memory bandwidth is included, but now it seems that it is not. VMAX's global memory bandwidth is 24*8=192GB/s. But this 50GB/s bidirectional bandwidth per engine is the original bandwidth without 8b/10b encoding.

But why 20K engine bandwidth is not 25GB/s, but 24GB/s, the netizen also did not know, but he at least let me figure out how 40K bandwidth is calculated.

As you know, the traffic within the engine is PCIE format, and these traffic must be encapsulated into RAPID IO format to communicate between different engines.

Although RAPID IO packaging efficiency is relatively high, but now PCIE switching technology has matured, but also support optical fiber connection, therefore, the next generation VMAX really does not need to use RAPID IO, which corresponds to our folk saying, take off pants fart, unnecessary. This is one of the reasons why Watermelon boldly predicted VMAX would abandon Rapio IO.

I have seen an official material these two days, EMC said that VMAX engine is composed of DMX components, with DMX genes.

As we discussed earlier, VMAX should be more about utilizing midrange storage CX/VNX platforms to form engines for cost reduction purposes. You see, the highlights of EMC's promotion of VMAX are also more from the price/performance ratio.

From the perspective of one engine architecture within EMC, the two Directors themselves employ CMI-II interconnects. This CMI is the famous CLARiiON Messaging Interface, which is used for communication between two controllers in the midrange controller and can be understood as a point-to-point high-speed PCIE bus.

In addition, we also learned that DMX originally used POWER PC architecture, but now VMAX is all INTEL chips. From this analysis, I think VMAX's engines share more of VNX/CX's hardware platforms, but the backend interface cards should still be redesigned because the backend interface cards are still FC-AL and do not use VNX's SAS connections.

As you know, CX old platform should be PCIE 1.0, VNX is PCIE 2.0. When VMAX was launched in 2009, the midrange was CX series, now VMAX's 10K and 40K should be upgraded to VNX's platform, but why is 20K still on the old platform? Is this also the reason why the bandwidth affecting the 20K engine is not 25GB/s but 24GB/s? It doesn't feel like it, because PCIE 1.0's bandwidth is 2.5G, PICE 2.0's bandwidth is 5G, twice the difference.

The above is what are the architectural difficulties of EMC VMAX shared by Xiaobian. If there are similar doubts, please refer to the above analysis for understanding. If you want to know more about it, please pay attention to the industry information channel.

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