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How to understand AXI Quad Serial Peripheral Interface IP core, many novices are not very clear about this, in order to help you solve this problem, the following small series will explain in detail for everyone, there are people who need this can learn, I hope you can gain something.

In the process of using MicroBlaze, this IP is called, so it must be carefully studied;

Noun:

XIP： eXecute In Place

Motorola M68HC11

Support features:

* Configurable AXI4 interface

* Support burst operation on DRR/DTR FIFO;

* Support configurable XIP mode operation;

* 32-bit Slave with AXI4-Lite or AXI4 interface;

* Support configurable SPI modes: standard, dual, quad mode;

* Programmable SPI clock phase and polarity;

* Configurable FIFO depth, 16, 256 depth; only support 64 depth for XIP mode;

*Configurable slave Memories in dual and quad modes are: Mixed,Micro,Winbond,and Spansion;

*SPICR

*SPI DTR：

After the SPE bit is set to 1 in master mode or spisel is active in the slave mode,the data is transferred from the SPI DTR to the shift register.

1. The DN-1 bit always indicates the MSB bit regardless of LSB first or MSB first transmission selection. When the transmission width parameter is 8 or 16, unused high bits ((AXI data width-1) to N) are reserved.

2. In standard SPI mode, the width of this register can be 8 or 16 or 32 depending on the core configuration. This register is 8 bits wide in dual or quad SPI mode.

*SPI DRR

The SPI data receive register (SPI DRR) is used to read data received from the SPI bus. This is a double buffer register. After each transmission, the received data is placed in this register. The SPI architecture does not provide any means for slaves to limit traffic on the bus; therefore, the SPI DRR is updated after each completed transaction only if the SPI DRR is read prior to the last SPI transfer. If the SPI DRR is not read and is full, the most recently transmitted data is lost and a receive overflow interrupt occurs. The same thing happens with master SPI devices.

*TX_FIFO_OCY:

The SPI transmit FIFO occupancy register (TX_FIFO_OCY) appears only when the AXI Quad SPI core is configured with FIFO (FIFO depth = 16 or 256). If it exists and the transmit FIFO is not empty, the register contains a four-bit right-aligned value that is one less than the number of elements in the FIFO (occupancy minus one).

This register is read-only. When writing, or reading when FIFO is empty, register contents are unaffected. The only reliable way to determine if the transmit FIFO is empty/full is to read the Tx_Empty / Tx_Full status bits in the SPI status register or the DTR empty bits in the interrupt status register.

*DGIER

Default [31]=0, global enable is disabled;

*IPIER

The interrupt enable register (IPIER) allows the system interrupt output to be asserted. This interrupt is generated if the valid bit in the IPISR register corresponds to the enable bit in the IPIER register. The IPIER register has an enable bit for each definition bit of IPISR. All bits are cleared on reset.

* Programming sequence:

Write enable command sequence:

1. Disable main transactions by setting the main disable bit of SPICR (60h) and reset RX and TX FIFO via SPICR.

Example: Write 0x1 E6 to SPICR

2. Issue the write enable command by writing 0x06 to SPIDTR.

3. Chip selection is issued by writing 0x00 to SPISSR (70h).

4. Enable main transactions by setting the SPICR main disable bit low.

5. Set the low selection by writing 0x01 to SPISSR.

6. Disable main transactions by setting the SPICR main disable bit.

Erase command sequence:

1. RX and TX FIFO reset via SPICR.

2. Send sector erase command (a) to SPIDTR to erase any specific sector following flash sector address or issue bulk erase command (a) to erase entire flash memory

Then there is the flash base address.

Example: Write 0xD8 to SPIDTR

3. Chip selection is issued by writing 0x00 to SPISSR.

4. Enable main transactions by setting the SPICR main disable bit low.

5. Set the low selection by writing 0x01 to SPISSR.

6. Disable main transactions by setting the SPICR main disable bit.

Write Data Command Sequence:

1. RX and TX FIFO reset via SPICR.

2. Send write data commands (a)(b) to SPIDTR to write data to any particular sector

Next is the flash sector address.

3. Fill SPIDTR with data to be written to flash; maximum data size depends on

QSPI FIFO size configured.

4. Chip selection is issued by writing 0x00 to SPISSR.

5. Enable main transactions by setting the SPICR main disable bit low.

6. Set the low selection by writing 0x01 to SPISSR.

7. Disable main transactions by setting the SPICR main disable bit.

Read Data Command Sequence:

1. RX and TX FIFO reset via SPICR.

2. Send a read data command (a)(b) to SPIDTR to read data from any particular sector

Next is the flash sector address.

3. Fill SPIDTR with dummy data to read the required data from flash memory.

4. Chip selection is issued by writing 0x00 to SPISSR (70h).

5. Enable main transactions by setting the SPICR main disable bit low.

6. Set the low selection by writing 0x01 to SPISSR.

7. Disables main transactions by setting the SPICR main disable bit

8. Read SPIDRR for read data received from SPI bus.

a. Refer to the appropriate SPI Slave data sheet for commands to issue.

b. Write/read commands vary depending on the mode used (standard/dual/quad).

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