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How to write the verilog code of testbench, in view of this problem, this article introduces the corresponding analysis and answer in detail, hoping to help more partners who want to solve this problem to find a more simple and easy way.

FPGA development board used: xilinx KC705

Development environment: vivado2019.1

Readme:

Yesterday, the "keystroke anti-shake" function was added to the code of the water lamp. The board is also tested, and the test results are OK.

However, for some board tests, sometimes they can not fully reflect the meaning of the logical design.

Therefore, it is still necessary for testbench to test the simulation waveform, through the waveform, whether it really fully expresses the original intention of the design.

Text:

1. The idea of compiling Test Files

In general, the process of writing a test file is as follows:

1) generate analog excitation (waveform)

2) add the generated incentive to the module under test and observe its response

3) compare the output response with the expected value

two。 How to write

1) establish the simulation file

File naming: file naming is consistent, followed by a suffix "tb" to indicate testbench.

At this point, an empty file comes out:

Write content

Learn about the basic architecture of testbench

Module Test_bench (); / / usually no input, no output / / signal or variable declaration definition / / input corresponds to reg type / / output in logic design corresponds to wire type reg key_in;// logic design, input corresponds to reg type reg rst_n;reg clk;reg [7:0] cnt;wire key_out;// logic design corresponds to wire type / / 1. Using initial or always statements to generate excitation / / generally includes: clock, reset, and (analog) generate test input signal / / 2. Instantiate the module key_noshake# (.cnt _ max (8'd100)) key_noshake_inst (.key _ in (key_in), .rst_n (rst_n), .clk (clk), .key_out (key_out)); / / 3. Monitoring and comparing the output response / / observing the output waveform after simulation can endmodule

3) the complete code is as follows:

`Here timescale 1ns / 1ps//// Company: / / Engineer: / Create Date: 2021-03-12 10 Design Name: / / Module Name: key_noshake_tb// Project Name: / / Target Devices: / / Tool Versions: / / Description: / / Dependencies: / Revision:// Revision 0.01-File Created// Additional Comments:// module key_noshake_tb () / / usually no input, no output / / signal or variable declaration defines reg key_in;// logic design input corresponds to reg type reg rst_n;reg clk;reg [7:0] cnt;wire key_out;// logic design corresponds to wire type / / 1. Use initial or always statements to generate incentives for initial begin clk=1'b1;rst_n=1'b0;#50rst_n=1'b1;endalways # 10 clk=~clk;// to generate (analog) clock signal always@ (posedge clk or negedge rst_n) if (rst_n==1'b0) cnt

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