Shulou(Shulou.com)12/24 Report--

CTOnews.com, December 21, Intel CEO Pat Kissinger (Pat Gelsinger) said in an interview recently that Intel's 18A process is comparable to TSMC's N2 process.

However, Kissinger said that in the back power supply (backside power delivery), Intel is better, and has been widely recognized by customers.

Kissinger said Intel provides better area efficiency in back power technology, which means lower costs and better power output, as well as higher performance.

Kissinger says the Intel 18A is slightly ahead of N2 with good transistors and strong power transmission. In addition, TSMC's packaging costs are higher, while Intel can provide a more competitive price advantage.

At present, TSMC, Intel and Samsung are all accelerating the promotion of contract manufacturing, and at the recent IEEE International Electronic equipment Conference (IEDM), all three companies demonstrated CFET (Complementary FET) transistor solutions.

CTOnews.com Note: the stacking CFET transistor architecture involves stacking two types of transistors (nFET and pFET) together, with the goal of replacing the fully surrounded gate (GAA) as a next-generation transistor design with double density.

Intel was the first contract manufacturer to showcase CFET solutions, releasing an early version as early as 2020, according to IEEE Spectrum. During the meeting, Intel introduced one of the simplest circuits made using CFET, focusing on the improvement of the inverter.

The CMOS inverter sends the same input voltage to the gate of the two transistors stacked together, producing an output opposite to the input logic, and the inverter is completed on a single fin.

Intel also improved the electrical characteristics of the CFET stack by increasing the number of nanowires per device from two to three and reducing the gap between the two devices from 50 nm to 30 nm.

Experts predict that from now on, the large-scale commercialization of CFET technology may take another seven to 10 years.

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