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This article will explain in detail the example analysis of STM32 interrupts for you. The editor thinks it is very practical, so I share it with you for reference. I hope you can get something after reading this article.

Interrupt plays a very important role in single-chip microcomputer. The code executes from top to bottom by default, and when it encounters a condition or other statement, it jumps to the specified place. In the process of single-chip microcomputer code execution, it is inevitable that there will be some unexpected situations that need to be dealt with, so that the current code will be interrupted. After dealing with the emergency, the program will return to the interrupted place to continue execution.

1 EXTI controller

The external interrupt / event controller (EXTI) manages 23 interrupt / event lines of the controller. Each interrupt / event line corresponds to an edge detector, which can realize the rising edge detection and falling edge detection of the input signal. EXTI can be configured separately for each interrupt / event line, and can be configured separately as interrupts or events, as well as properties that trigger events.

The external signal enters the edge detection circuit that passes through 1, detects whether it conforms (determined by the rising and falling edge selection registers of 2 and 3), and then generates a signal with 4 software interrupt event registers or values (that is, software interrupt event registers can be written into software interrupt event registers to simulate interrupts and events), after which the signal is divided into two, see 5 interrupt masking register and 7 event masking register If both interrupts and events are not shielded, events will first be generated and enter the pulse generator. Second, it will enter the 6 pending register and then enter the NVIC.

Note:

1. As mentioned above, we can use register 4 software to simulate the entry of signals with qualified interrupt event register mode, why can't we use 6 registers? Because

Registers are readable and erasable registers that are cleared by writing 1. Writing 0 is not valid. So you can't use it.

2. With regard to suspending registers, suspending means that if there is an interrupt, it will trigger the interrupt. But there will be no hardware cleanup.

It can only be cleared by software, or when the edge polarity is modified. As follows

Let's start with EXTI.

The main features of the EXTI controller:

Each interrupt / event has an independent trigger and mask on the line.

Each break line has a dedicated status bit.

Support for up to 23 software event / interrupt requests

Detect an external signal whose pulse width is lower than the clock width of APB2

The following is a frame diagram of ST207.

It can be seen from the diagram that the registers related to external interrupts are: rising edge trigger selection, falling edge trigger selection, software interrupt event register, interrupt masking register, pending request register, event masking register and NVIC interrupt control register. In addition, there is the understanding of the input line.

The other seven EXTI lines are connected as follows

EXTI is an external interrupt, the above is mainly for the description of these 22 interrupt lines, we also know that there are still a lot of interrupts, such as timer interrupts, serial port interrupts and so on, they do not belong to these 22 interrupt lines.

We can see it in the interrupt vector scale.

Other interrupt configurations are in the registers of each module.

2 NVIC controller

After the above EXTI registers are set, you can set NVIC. There is less description in the chip programming manual about NVIC, but it says

So let's just refer to the M3 manual.

Find the AIRCR register, where 8 to 10 bits are priority packets

The library function we use in the code is

Void NVIC_PRIGroup_Enable (uint32_t NVIC_PRIGroup) {/ * Set the priority grouping value * / SCB- > AIRCR = AIRCR_VECTKEY_MASK | NVIC_PRIGroup;}

In which we found out

1. The address of SCB- > AIRCR in the library function is 0XE000ED0C. If you don't know how to query it, please check Baidu by yourself.

2. Find the structure definition of SCB

We see that SCB is the abbreviation of SystemControl Block.

Let's talk about the value of the grouping.

There is in misc.c

* = * NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description * = * NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority * | | | | 4 bits for subpriority *-| -* NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority * | 3 bits for subpriority *- - -* NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority * | 2 bits for subpriority *- -* NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority * | 1 bits for subpriority *- -* NVIC_PriorityGroup_4 | 0-15 | | 0 | 4 bits for pre-emption priority * | 0 bits for subpriority * = |

Preemption priority & response priority difference

A high priority preemption priority can interrupt ongoing low preemption priority interruptions.

To preempt interrupts with the same priority, high response priority cannot interrupt interrupts with low response priority.

Preempt interrupts with the same priority. When two interrupts occur at the same time, which response has the highest priority and which is executed first.

If the preemptive priority and response priority of both interrupts are the same, which interrupt occurs first will be executed first.

Example:

Suppose you set the interrupt priority group to 2, and then set the

Interrupt 3 (RTC interrupt) has a preemptive priority of 2 and a response priority of 1.

Interrupt 6 (external interrupt 0) has a preemptive priority of 3 and a response priority of 0

Interrupt 7 (external interrupt 1) has a preemptive priority of 2 and a response priority of 0.

Then the priority order of the three interrupts is: interrupt 7 > interrupt 3 > interrupt 6.

Manifested in the code

NVIC_InitPara NVIC_InitStructure;NVIC_InitStructure.NVIC_IRQ = IRQn;NVIC_InitStructure.NVIC_IRQPreemptPriority = pri;NVIC_InitStructure.NVIC_IRQSubPriority = pri1;NVIC_InitStructure.NVIC_IRQEnable = ENABLE;NVIC_Init (& NVIC_InitStructure)

Group 0, then the range of values of pri is 0, 0, and the range of values of primer 1, 0, 16.

Group 2, then the range of values of pri is 04th, and the range of values of primer 1 is 04th.

Grouping 4, then the range of values of pri is 0such 16 and the range of values of primer 1 is 0 zero.

Let's talk about the NVIC register.

_ _ IO uint8_t IP [240,240]; / / Register group for interrupt priority control

_ _ IO uint32_t ISER [8]; / / interrupt enable register group

_ _ IO uint32_t ICER [8]; / / interrupt disability register group

_ _ IO uint32_t ISPR [8]; / / interrupt pending register group

_ _ IO uint32_t ICPR [8]; / / interrupt unhang register group

_ _ IO uint32_t IABR [8]; / / interrupt activation flag bit register group

Interrupt priority controlled register group: IP [240]

Full name is: InterruptPriority Registers

There are 240 8-bit registers, one for each interrupt to determine priority.

For example: STM32F10x series has a total of 60 masked interrupts, using IP [59] ~ IP [0].

The upper 4 bits of each IP register are used to set preemption and response priorities (based on grouping), while the lower 4 bits are not used.

Void NVIC_Init (NVIC_InitTypeDef* NVIC_InitStruct)

Interrupt enable register group: ISER [8]

Function: used to enable interruption

32-bit registers, each bit controls the enabling of an interrupt. STM32F10x has only 60 masked interrupts, so only ISER [0] and ISER [1] are used.

The bit0~bit31 of ISER [0] corresponds to interrupt 0x31, respectively. Bit0~27 corresponding interrupt 3259 for ISER [1]

Void NVIC_Init (NVIC_InitTypeDef* NVIC_InitStruct)

Interrupt disability register group: ICER [8]

Function: used for disability interruption

32-bit registers, each bit controls the disability of an interrupt. STM32F10x has only 60 masked interrupts, so only ICER [0] and ICER [1] are used.

The bit0~bit31 of ICER [0] corresponds to interrupt 0x31, respectively. Bit0~27 corresponding interrupt 3259 for ICER [1]

The configuration method is the same as ISER.

Void NVIC_Init (NVIC_InitTypeDef* NVIC_InitStruct)

Interrupt pending control register group: ISPR [8]

Function: used to suspend interrupts

Interrupt unhang control register group: ICPR [8]

Function: used to unhook interrupts

Static _ INLINE void NVIC_SetPendingIRQ (IRQn_Type IRQn); static _ INLINE uint32_t NVIC_GetPendingIRQ (IRQn_Type IRQn); static _ INLINE void NVIC_ClearPendingIRQ (IRQn_Type IRQn)

Interrupt activation flag bit register group: IABR [8]

Function: read-only, through which you can know which interrupt is currently being executed

If the corresponding bit is 1, the interrupt is being executed.

Static _ _ INLINE uint32_t NVIC_GetActive (IRQn_Type IRQn) 3 code

Be sure to enable the system clock

Because SYSCFG is required to configure the mapping between GPIO and interrupt lines

SYSCFG_EXTILineConfig (EXTI_PortSourceGPIOE, EXTI_PinSource11)

Whenever an external interrupt is used, be sure to turn on the SYSCFG clock

Open source code address:

Https://github.com/strongercjd/STM32F207VCT6/tree/master/09-EXTI

This is the end of this article on "sample Analysis of STM32 interrupts". I hope the above content can be helpful to you, so that you can learn more knowledge. if you think the article is good, please share it for more people to see.

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