Shulou(Shulou.com)12/24 Report--

Thanks to CTOnews.com netizen OC_Formula for the clue delivery! CTOnews.com December 7, Renesa Electronics announced today that it has successfully designed, tested and launched a 32-bit CPU kernel based on the open standard RISC-V instruction set architecture (ISA).

According to reports, Renesas, as the first manufacturer in the industry to independently develop the CPU kernel for the 32-bit general RISC-V market, has created an open and flexible platform for the Internet of things, consumer electronics, health care and industrial systems. The new RISC-V CPU kernel will expand Renesas's existing 32-bit microcontroller (MCU) IP product line, including proprietary RX product families and RA product families based on Arm Cortex-M architecture.

RISC-V is an open ISA, which is rapidly popularized in the semiconductor industry because of its flexibility, scalability, high energy efficiency and open ecosystem. At present, many MCU suppliers have established joint investment alliances to speed up the development of RISC-V products.

According to Renesas, this multi-functional CPU can be used as a primary application controller, as well as an auxiliary core in SoC, on-chip subsystems, and even deep embedded ASSP, with CoreMark / MHz performance up to 3.27. (CTOnews.com Note: CoreMark / MHz refers to the number of times a CoreMark program is run per unit time. ARM Cortex-M3 's figure is 3.32, which means the performance is about the same.)

CTOnews.com learned from the official blog that Renesas is providing some customers with samples based on the new kernel and plans to launch the first RISC-V-based MCU and related development tools in the first quarter of 2024, when details of the new MCU products will also be announced.

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