Shulou(Shulou.com)11/24 Report--

CTOnews.com Nov 1, according to DigiTimes, Samsung Foundry Vice President Jeong Gi-Tae revealed that Samsung will soon launch SF1.4 (1.4nm) process, the number of nanosheets has increased from 3 to 4, which is expected to significantly improve performance and power consumption.

Samsung is seeking to expand its leading position in the Gate-All-Around (GAA) platform and, following the launch of the GAA-based SF3E, plans to launch the SF1.4 (1.4nm) process in 2027 to further improve the process by increasing the number of nanowires.

Increasing the number of nano-wafers per transistor can enhance the driving current, thus improving performance, and more nano-wafers allow more current to flow through the transistor, thus enhancing its switching ability and running speed.

In addition, more nanowires can better control the current, which helps to reduce the leakage current, thus reducing power consumption. In addition, improved current control means that transistors generate less heat, thereby improving power efficiency.

CTOnews.com previously reported that Samsung also plans to use back power (BSPDN) technology in the 1.4nm process to better tap the potential of the space on the back of the wafer, but it has not yet been implemented on a global scale.

Although the semiconductor industry no longer uses gate length and metal half-pitch to name technology nodes systematically, there is no doubt that the smaller the number, the more advanced the current process technology.

As the miniature route of semiconductor technology continues to move forward, the distance between circuits in integrated circuits continues to narrow, resulting in interference to each other, and BSPDN technology can overcome this limitation, because we can use the back of the wafer to build power supply lines to separate circuits and power space.

Related readings:

"Samsung plans to use BSPDN back power technology in 1.4nm process in 2027."

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