Shulou(Shulou.com)11/24 Report--

CTOnews.com, October 24 (Xinhua)-- designing chips is usually a time-consuming and costly task, which usually costs more than $100 million (CTOnews.com Note: currently about 731 million yuan) and takes at least 3 years from concept to production. Zero ASIC hopes to automate chip design by using a code-free approach.

The company launched the ChipMaker platform, which uses a small chip-based design to simplify the process and hide the complexity of the circuit design, enabling users to quickly and accurately test and modify their custom designs before ordering physical equipment.

The automation platform, mainly based on eFabric (grid 3D mediator that allows interconnection between chips) and eBrick (a group of prefabricated 3D chipsets with plug and play), uses cloud field programmable gate array (FPGA) to modify the RTL source code.

EBrick includes dual-core processors supporting quad-core RISC-V Linux, 5K LUT embedded FPGA and 3MB SRAM-3 TOPS machine learning accelerator.

Andreas Ologsson, chief executive and founder of Zero ASIC, said: "in order to build the next wave of world-changing silicon devices, we need to lower the threshold of ASIC by several orders of magnitude. Our Zero ASIC mission is to make ASIC ordering possible as simple as ordering catalog parts from electronics dealers."

The company says designing chips using the ChipMaker platform costs only one-tenth or one-100th of the conventional cost and can be used in areas such as robotics, car safety, aviation, defense and 5G and 6G communications.

The company says it won't provide samples until at least the third quarter of 2024, so companies such as Nvidia and Intel don't have to worry that Zero ASIC products will erode their market share.

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