Shulou(Shulou.com)11/24 Report--

Thanks to CTOnews.com netizen OC_Formula for the clue delivery! CTOnews.com, October 15, according to Samsung's official news, HBM memory for high performance computing (HPC) has ushered in new developments. 9.8Gbps 's HBM3E product has begun to provide customers with samples, while HBM4 memory is expected to be launched in 2025.

Although there is no formal specification for HBM4, TSMC has given some of the standards under development at the 2023 OIP Forum Amsterdam plant. TSMC said that in the future, the interface width of HBM4 memory will double to 2048 bit.

It is worth mentioning that for a variety of technical reasons, they also hope to achieve this goal without increasing the footprint of the HBM memory stack, which will double the interconnect density of the next generation of HBM memory without further improving clock speed.

According to the plan, this will enable HBM4 to make a major leap forward on a variety of technical levels.

In terms of DRAM stacking, a 2048bit memory interface requires a significant increase in the number of silicon via holes. At the same time, the external chip interface will need to reduce the bump spacing to less than 55 microns, while significantly increasing the number of microbumps (CTOnews.com Note: HBM3 currently has about 3982 microbumps).

In addition, HBM4 will adopt 16-Hi stacking mode, that is, stacking 16 memory chips in a module, which will further increase its technical complexity (HBM3 also supports 16-Hi stacking at a technical level, but so far no manufacturer has actually done so).

All these new indicators, in turn, require closer cooperation between chipmakers, memory manufacturers and chip packaging companies to ensure that everything goes smoothly.

At TSMC's TSMC OIP 2023 conference in Amsterdam, Dan Koch Pacharin, TSMC's head of design infrastructure management, said: "because they didn't double the speed, they doubled the [interface] pins [with HBM4]. This is why we are working to ensure that we work with all three partners to qualify their HBM4 [can pass our advanced packaging] and that RDL or mediators or anything in between can support the layout and speed of HBM4. So we are working with Samsung, SK Hynix and Micron. "

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