Shulou(Shulou.com)11/24 Report--

Thanks to CTOnews.com netizen OC_Formula for the clue delivery! CTOnews.com, October 12, according to Samsung's official blog, HBM memory for high performance computing (HPC) has ushered in new developments. It will develop 9.8Gbps 's HBM3E product and has begun to provide samples to customers.

In addition, HBM4 memory is under development for 2025, and NCF assembly technology and HCB technology optimized for high-temperature thermal characteristics are being prepared for this product.

CTOnews.com Note: NCF (Non-conductive Film, non-conductive film): polymer layer (Polymer layer) used to protect solid-state joints (Solder joint) between laminated chips from insulation and mechanical shock.

HCB (Hybrid Copper Bonding, mixed bonding): as a new generation of bonding technology, copper (conductor) and oxide film (insulator) are bonded instead of traditional welding.

At the beginning of this year, Samsung AVP (Advanced Packaging) business team was established to enhance cutting-edge packaging technology and maximize synergies between business units. Samsung plans to work with HBM to provide cutting-edge customized packaging services, including 2.5D and 3D cutting-edge packaging solutions.

Samsung says high-end CPU for AI services requires more than 100 cores, each with enough memory. In addition, in order to load more capacity in a limited package, the process technology to minimize the single chip size of the DRAM and the design technology to correctly place the components within the form factor and ensure that they operate according to specifications are also critical.

Samsung released 32Gb DDR5 DRAM memory last month, which achieved twice the capacity of 16Gb DRAM through architectural improvements of the same package size, allowing 128GB modules to be manufactured without a TSV process. This makes it possible to reduce costs and increase productivity, while reducing power consumption by 10 per cent, Samsung said.

TSV (Through Silicon Via): a packaging technology that thinns a chip, drills out hundreds of small holes, and connects electrodes that pass vertically through the holes in the top and bottom of the chip.

Samsung said at the end of its blog that it will continue to overcome technical limitations and develop a variety of memory solutions unprecedented in the world in the future. In particular, Samsung plans to develop ultra-high performance, ultra-high capacity and ultra-low power consumption memory products in the AI era based on less than 10 nm technology, and claims that "will be a major inflection point in the DRAM market."

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