Shulou(Shulou.com)11/24 Report--

CTOnews.com, Oct. 11, Samsung Electronics began mass production of 3nm chips in June last year, but there are few customers, and it seems that only one unnamed Chinese customer has made the order so far.

ADTechnology, a South Korean semiconductor design company, has announced that it has signed a contract with an overseas customer for a server-oriented chip design project based on Samsung's 3nm process. This is also the first time that Samsung Electronics has confirmed that it has won 3nm customers through a design company.

ADTechnology does not identify the customer, but is said to be an American company that specializes in high-performance computing (HPC) chips.

"We are pleased to announce a partnership with our reliable partner ADTechnology on the 3nm design project," said Gibong Jeong, executive vice president and head of the business development team for Samsung wafer foundry. "our joint efforts will be an excellent example of collaboration within the SAFE ecosystem. We look forward to the opportunity to work more closely together to provide excellent products to our customers."

JK Park, CEO of ADTechnology, said: "this 3nm project will be one of the largest ASIC products in the industry. I believe that this 3nm and 2.5D design experience will be a good medicine for us to distinguish ourselves from our competitors in the future. We will do our best to provide our customers with high-quality design solutions."

Different from the fin field effect transistor (FinFET) architecture used in 7nm, 5nm and other processes, Samsung Electronics 3nm process takes the lead in using full surround gate transistor GAA architecture.

Samsung Electronics said that compared with the 5nm process, the chips made by their first-generation 3nm process achieved 45% energy efficiency improvement compared to 5nm, 23% performance improvement and 16% area reduction (PPA). In addition, Samsung's new generation 3nm process SF3 has achieved a 22% frequency increase, 34% energy efficiency improvement and 21% area reduction compared with the 4nm FinFET platform.

Samsung will focus on 3nm production in 2023-2024, namely SF3 (3GAP) and its improved version SF3P (3GAP+). Its production yield can be maintained in the initial range of 60-70%, and the company plans to launch its 2nm-level nodes in 2025-2026.

After Samsung and TSMC have entered the era of 3nm process, 3nm process will become the mainstream of wafer foundry market in the future. As a result, the 3nm process market is expected to be worth as much as $25.5 billion by 2025 (CTOnews.com Note: currently about 176.205 billion yuan), surpassing the $19.3 billion estimated at the time of 5nm.

In the third quarter of 2022, TSMC still ranks first in the global wafer foundry market with a market share of 53.4%, while Samsung, which ranks second, has a market share of 16.4%, according to TrendForce, a market research firm based on Tu Yuan Unsplash. Therefore, in the fierce competition in the market, the 3nm process will become the key to the main competition between the two companies in the future.

Related readings:

"sources say that Samsung and TSMC have a 3nm quality rate of about 50%, which is expected to affect order competition next year."

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