Shulou(Shulou.com)11/24 Report--

CTOnews.com September 6 news, recently, the Arctic male core announced that the first self-developed Chiplet interconnection interface based on the domestic "core interconnection interface standard" PBLink chip test success. PBLink interface has the characteristics of low cost, low delay, high bandwidth, high reliability, in line with domestic interface standards, compatible with internal and external interconnection, and pays attention to domestic self-control.

According to reports, the interface is manufactured by 12nm technology, and each D2D unit is designed for 8 channels, which provides the highest 256Gb / s transmission bandwidth, fewer packaging interconnects can be used to reduce the packaging requirements, and at least three layers of substrates are needed for 2D interconnection.

▲ Arctic male core 256Gb / s bandwidth of the D2D test chip back test is successful, the picture source Arctic male core official account, which is also based on specially optimized reduced protocol layer and physical layer, this interface can achieve end-to-end delay at the ns level, and all indicators meet the requirements of the Core Interconnection Interface Standard and design expectations.

In addition, PB Link can flexibly support in-package Chiplet-Chiplet interconnection and 10-15cm package board-level Chip-Chip interconnection, flexibly adapting to various downstream application scenarios.

Arctic male Core said that the company took the lead in introducing a core solution based on traditional packaging (153 μ m Standard Package) and expects to launch a high-density interconnection version (55 μ m InFO Package) for ultra-high performance scenarios in 2024-2025.

In addition, the PB Link successfully tested this time will be used on the company's next-generation core HUB Chiplet and some functional Chiplet, and is expected to achieve overall mass production by 2024.

According to previous reports from CTOnews.com, the Arctic male Core released the first artificial intelligence computing chip "Qiming 930" based on Chiplet heterogeneous integration at the beginning of this year. The central control core uses RISC-V CPU core and can carry multiple functional core particles through a high-speed interface, based on national substrate materials and 2.5D packaging.

Chiplet architecture refers to the production and integrated packaging of large chips into small core particles, which can effectively improve the comprehensive yield of large computing chip manufacturing, and create flexible collocation choices through core particle reuse. At present, Intel and AMD products adopt related technology, which is an improvement scheme of traditional single chip.

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