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This article introduces what the role of $cast method in SystemVerilog is, the content is very detailed, interested friends can refer to, hope to be helpful to you.

Cast is a built-in method in systemverilog.

Cast can convert different built-in types, more often between different levels of classes. In this conversion between a parent class and a child class, the parent class stands high and the child class is at the bottom, and the conversion from the parent class to the child class is called down type conversion, while the conversion from child class to parent class is called up type conversion. Upward typing is safe, and vice versa. The reason is that since the subclass inherits the parent class, it has all the attributes of the parent class. in addition, the dragon gives birth to nine children, each of which is different, and the subclass has its own unique personality, which the parent class does not have. When doing an upward conversion, the handle equivalent to the parent class points to the subclass object, so that the handle can still access the properties of the subclass object that are the same as the parent class. But conversely, if the downward conversion is so free, what happens when you try to point the handle of the subclass to the object of the parent class? The parent class originally marked a small piece of territory, but because the subclass contains richer attributes than the parent class, it is likely to access resources that the parent class does not contain, then the resource can not be found, out of bounds, so there will be error. The parent class is like Shanghai, and the subclass is equivalent to the Yangtze River Delta region, including but not just Shanghai, so the subclass can go wherever the parent class can go, and vice versa, so it doesn't matter to give the handle of the subclass to the parent class, but not vice versa. So downward types need strict type checking to prevent illegal conversion.

Ex1:

Class father; string m_name

Function new (string name); m_name = name; endfunction: new

Function void print (); $display ("Hello% s", m_name); endfunction: printendclass: father

Class child1 extends father; string area1 = "jiangzhehu"

Function new (string area1); super.new (area1); endfunction: newendclass: child1

Class child2 extends father; string area2 = "shanghai"

Function new (string area2); super.new (area2); endfunction: newendclass: child2

Program top; father f; child1 c10, c11, c12; child2, c20, c21, c22.

Initial begin f = new ("shanghai"); f.print (); c10 = new ("jiangzhehu"); f = C10; f.print (); C20 = new ("changsanjiao"); f = c20; f.print (); c20.area2 = "zhejiang"; $cast (c21, f) C21.print (); $display ("has% s", c21.area2); C22 = C20; c22.print (); $display ("has% s", c22.area2); c20.area2 = "hangzhou"; c21.print (); $display ("has% s", c21.area2); c22.print () $display ("has% s", c22.area2)

End endprogram: top

The simulation results are as follows:

# Hello shanghai# Hello jiangzhehu# Hello changsanjiao# Hello changsanjiao# has zhejiang# Hello changsanjiao# has zhejiang# Hello changsanjiao# has hangzhou# Hello changsanjiao# has hangzhou

Note that you cannot directly assign $cast (c21, f); only if the subclass is assigned to the parent class first.

You can't give c20 to c10 with cast

On the role of the $cast method in SystemVerilog is shared here, I hope the above content can be of some help to you, can learn more knowledge. If you think the article is good, you can share it for more people to see.

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