Shulou(Shulou.com)11/24 Report--

Thanks to CTOnews.com netizens Wu Yanzu in South China for the delivery of clues! CTOnews.com July 25, Intel today released a new advanced performance extension instruction set (APX) and introduced a new AVX10 instruction set that will provide unified AVX-512 support for P and E cores.

To put it simply, AVX10 (Advanced Vector Extensions 10) ISA is a superset of AVX-512 and has all the AVX-512 ISA functions of 256bit and 512bit register size.

CTOnews.com warns that this new instruction set is not supported by Intel CPU for the time being-it is expected to appear in future chips, including "Granite Rapids". Intel said AVX10 will be its vector ISA of choice for future consumers and server processors.

At the most basic level, AVX10 will enable Intel chips with both E and P cores to support AVX-512. Although the 512bit version can only run on P cores, 256bit's AVX-256 analog instruction set can run on both P cores and E cores.

According to reports, AVX10 will include "AVX-512 vector instructions with AVX512VL function logo, maximum vector register length of 256bit and eight 32bit mask registers, and new 256bit instructions that support embedded rounding."

This version can be run on P and E cores, but E cores are limited to the maximum 256bit length, while P cores can use full 512bit vectors, similar to Arm's support for variable vector width through SVE.

Intel said that the performance of existing applications on AVX10 is the same as that of AVX-512, at least in the same vector length. Intel also claims:

Applications compiled by Intel AVX2 can achieve performance improvements without additional software adjustments when recompiled to AVX10.

Intel AVX2 applications that are pressure sensitive to vector registers can achieve significant performance improvements thanks to the addition of 16 new vector registers and new instructions.

Highly threaded, vectorizable applications may achieve higher overall throughput when using Intel Xeon E core-based processors or Intel products with hybrid architectures.

In the future, Intel will provide Meteor Lake for consumer customers and Granite Rapids and Sierra Forest for HPC customers, and all three series adopt a similar architecture, with P core as Redwood Cove core and E core based on Crestmont architecture.

It is reported that Intel will support the first version of AVX10 (AVX10.1) from the sixth generation of Xeon "Granite Rapids" chips, but this version only supports 512bit vector instructions, not the new 256bit vector instructions.

In other words, this generation is only used as a transition chip from AVX-512 to AVX10. However, all future Xeon processors themselves will continue to support full AVX-512 instructions to ensure the proper operation of traditional applications.

Subsequent AVX10.2 will support 256bit vector length and other new features, such as new AI data types and conversions, data movement optimization, and standard support.

To address developers' concerns, Intel also plans to implement greatly simplified enumerations for AVX10 compared to AVX-512, and to ensure that there are enough new instructions and features worth upgrading every time you move to a new revision, so as to reduce version and enumeration expansion.

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