Shulou(Shulou.com)11/24 Report--

The chip carries the most advanced technology of mankind. Nowadays, China has become a powerful country in chip design, but it has been stuck everywhere in chip manufacturing. What is the difficulty in chip manufacturing?

Today, the chip has formed a very mature and specialized manufacturing process [1], which is not simply achieved in one step, but divided into multiple stages with a certain time interval and space order [2]. Generally speaking, chip manufacturing is divided into three major links: wafer processing, front process (chip processing) and back process (packaging and testing). Our country mainly focuses on wafer processing and manufacturing, and back packaging and testing. Most of the high-end equipment and materials in the front process are basically blank, so high-end chips often need to be imported. [3]

This article is the 24th article in the series of "domestic substitution" planned by "Fruit Shell hard Technology", which focuses on the whole process of semiconductor manufacturing. In this article, you will learn about the technical details of the whole semiconductor manufacturing process, what equipment and materials are involved in the semiconductor manufacturing process, and the development of the semiconductor manufacturing process inside and outside China.

Fu Bin | author

Li Tuo | Editor

1. Wafer manufacturing: first wafer and then core. If you want to get a chip, you must first make a thin wafer of quartz sand (or substrate), then carry out subsequent processing, and finally cut it into a chip.

Therefore, wafer processing and manufacturing is the upstream and basic industry of the semiconductor industry, which is divided into three sub-industries: preliminary purification of silicon, monocrystalline silicon manufacturing and wafer manufacturing.

The production process of integrated circuits: from quartz sand to chip [4] wafers and Weihua biscuits are all wafer in English, this is no coincidence. For example, producing wafers is like producing crackers, sifting the flour, mixing it with seasoning and water, stirring it into dough, roller printing it into cake germ, and then cutting it. The same is true of wafer manufacturing, except that wafer manufacturing requires extremely stringent raw materials and processes.

Because silicon accounts for 25.8% of the earth's crust, it is rich in reserves and easy to obtain, so silicon-based semiconductors are the most productive and widely used semiconductor materials. However, not all silicon can be used as chips, and the scale of the chip manufacturing process has reached the nanometer level, and any fine impurities will affect the normal operation of the chip. therefore, the silicon used in chip manufacturing is high-purity polysilicon with a purity of 99.99999999% (911 9).

Different chips require different types of wafers, just like producing crackers with different flavors. According to different indicators, wafers are divided into many types.

Classification of semiconductor silicon wafers [5] according to the process, wafers can be roughly divided into three categories: polished wafers, epitaxial wafers and SOI wafers. No matter what kind of wafer is made, its origin is polished, because other types of wafers are products of secondary processing on the basis of polished wafers, such as annealing on the basis of polished wafers, which can have very complicated branches.

Main types and characteristics of wafers, tabulation (fruit shell hard science and technology)

Source: Shanghai Silicon Industry prospectus [6]

The production processes of different types of wafers are extremely complex:

The production process of polishing wafer includes crystal drawing, rolling, cutting, grinding, etching, polishing, cleaning and so on.

Compared with other processes, each wafer costs only $1, and each wafer costs about $20,100 for epitaxial growth, so the epitaxial process is one of the most expensive processes in integrated circuit manufacturing [7]. Epitaxial wafers are mainly grown on the basis of polished wafers

SOI films are mainly made by bonding or ion implantation. [6]

Process flow chart of semiconductor polished wafer and epitaxial wafer [6]

The technological process of SOI wafers [6] according to the diameter, the wafers are divided into 2 inches (50mm), 3 inches (75mm), 4 inches (100mm), 5 inches (125mm), 6 inches (150mm), 8 inches (200mm) and 12 inches (300mm).

The larger the wafer size, the more chips can be made per wafer, and the lower the cost per chip. Like a cake, the bigger the cake, the more small pieces of the same size can be cut out.

In addition, when you cut a chip on a wafer, some edge areas cannot be used. Imagine that when you cut a square on a wafer, it is impossible to cut a complete square on the edge. No matter which kind of wafer is used, the chip size specification has been fixed, so the larger the wafer size, the smaller the wafer edge loss, and the large size wafer can further reduce the chip cost.

So, since there are so many areas on the edge of the round wafer that cannot be used, why not make it a "crystal square"? In fact, it is not that scientists have not thought about this problem, but are subject to technological limitations and become a problem left over by history.

First of all, the silicon rod grown by the single crystal is cylindrical and becomes round after being cut into thin slices; secondly, the cylindrical single crystal silicon ingot is more convenient for transportation to avoid material loss caused by bumping; in addition, the circular object is convenient for the operation of the following steps; finally, even if the crystal is made into a square, some edges are still not available, and the calculation shows that the circular edge is less wasteful than the square. [8]

Global percentage of shipped area of wafers of different sizes [6] take 8-inch and 12-inch silicon polished wafers as an example, under the same process conditions, 12-inch wafers can use more than twice the area of 8-inch wafers. Availability (a measure of the number of chips that can be produced per wafer) is about 2.5 times that of 8-inch silicon wafers. [6]

Of course, the larger the size of the wafer, the more difficult it is to make, and the more requirements for production technology, equipment, materials and processes. Specifically, the key technical indicators include local flatness, local edge flatness, nano-morphology, oxygen content, height radial second derivative and so on. however, the advanced process has higher requirements for wafer warping, curvature, resistivity, surface metal residue and other parameters.

Comparison between 8-inch polishing wafer and 12-inch polishing wafer [6] not only silicon can be made into wafers, at present, semiconductor materials have developed to the fourth generation. The first generation semiconductor materials are represented by Si (silicon) and Ge (germanium), the second generation semiconductor materials are represented by GaAs (gallium arsenide) and InP (indium phosphide), the third generation semiconductor materials are represented by GaN (gallium nitride) and SiC (silicon carbide), and the fourth generation semiconductor materials are represented by aluminum nitride (AlN), gallium oxide (Ga2O3) and diamond (C).

However, more than 90% of the chips still need to use semiconductor wafers as substrates.

Throughout the global wafer market, the global wafer market is mainly occupied by international manufacturers with a high degree of concentration. In 2021, the global wafer market CR5 is 94%. The top five manufacturers are Japan Shinyue Chemical (Shin-Etsu), Japan Shenggao (SUMCO), Taiwan Global Wafer (Global Wafers), Germany's Siltronic, and South Korea's Xianjing Silicon Tyrone (SK Siltron). [9]

On the domestic side, the technology is weak, the business scale is small, the concentration is low, and most of the products are 8 inches or less. Domestic semiconductor wafer enterprises mainly include Shanghai Silicon Industry, Central shares, Lion Micro, Zhongjing Technology, Youyan Silicon, Musk and so on. Single manufacturers have a market share of no more than 10%, and mainly 8-inch or less silicon wafers. 12-inch wafers are the focus of China's industry in the past two years: for example, Yuexin Semiconductor is a 12-inch chip manufacturer specializing in analog chips and entering full mass production, with a total investment of 37 billion yuan [10]. Core technology monthly processing 20,000 12-inch smart sensor wafer production line project, a total investment of 7 billion yuan. [11]

According to the data, the market size of domestic silicon wafers has continuously exceeded US $1 billion from 2019 to 2021, reaching US $1.656 billion in 2021, an increase of 24.04% over the same period last year, and is expected to reach US $1.922 billion in 2022. [12]

Global wafer market pattern in 2021 [9] from the global second generation semiconductor (GaAs, InP) substrate and the third generation semiconductor (GaN, SiC) substrate, there are a large number of related enterprises in China, but there is a gap between the overall production capacity and the international scale.

Comparison of global market and domestic development of second-generation semiconductors and third-generation semiconductor wafers, tabulation (fruit shell hard technology)

Reference material: SIMIT Strategic Research Office [13]

2. Previous process: equipment stacking process "this is like the paradise I imagined." it's just that there are more robots. " This is an expert's evaluation of semiconductor manufacturing plants. [14]

First of all, there is equipment to talk about manufacturing, in the fab capital expenditure, wafer processing equipment capital expenditure is also the largest, accounting for 70%-80%. [15]

Typical capital expenditure structure in the field of integrated circuit manufacturing [15] in the process of chip production, thousands of process equipment are running at the same time, it can be said that it is difficult to build equipment, which makes it more difficult for these equipment to be produced in an orderly manner.

The pre-chip processes include lithography, dry etching, wet etching, chemical vapor deposition, physical vapor deposition, plasma washing, wet cleaning, heat treatment, electroplating, chemical surface treatment and mechanical surface treatment, many of which will be used repeatedly. Very complicated.

Each pre-process corresponds to the corresponding equipment, including lithography machine, glue developer, etching machine, film deposition equipment, ion implantation equipment, heat treatment equipment (oxidation annealing equipment), chemical and mechanical sharing (CMP) equipment, cleaning equipment, process testing equipment, etc.

Schematic diagram of semiconductor manufacturing and semiconductor material industry [9] in the pre-processing, the equipment is mainly selected around the manufacturing process, that is, 28nm, 14nm, 10nm, 7nm, 4nm, 3nm, which are often mentioned. The smaller the manufacturing process, the more difficult it is to manufacture and the higher the equipment requirements. At present, 28nm is a watershed in the industry. What is more advanced than 28nm is the advanced process, otherwise it is the mature process.

The process iterates with Moore's Law, that is, the number of transistors on the chip doubles every 18 to 24 months, and the performance doubles.

In the International equipment and Systems Roadmap (IRDS), it comprehensively reflects the new system-level technologies required by each process node, that is to say, what equipment is needed for the most advanced process in the next few years has been decided, and IRDS will be constantly updated with process upgrades.

Technical planning for future process nodes in IRDS [16] in terms of value component, lithography, etching and thin film deposition are the three most important links in pre-processing. In 2021, lithography, etching and thin film deposition equipment (including CVD, ALD, PVD) accounted for 20%, 25% and 22% respectively, accounting for 60% of the total expenditure. [17]

Global semiconductor equipment value distribution in 2021 [17] throughout China's different equipment localization rate, although the overall upward trend, but the overall localization rate is still low, the upstream production capacity is very weak.

Overview of domestic semiconductor manufacturing equipment, tabulation (fruit shell hard technology)

Reference materials: Guohai Securities [18]

In the following, fruit shell hard technology will analyze in detail the nine kinds of equipment with the highest value, such as lithography machine, glue developer, etching machine, film deposition equipment, heat treatment equipment (oxidation annealing equipment), ion implantation equipment, chemical and mechanical sharing (CMP) equipment, cleaning equipment and process testing equipment.

Lithography machine is the largest, most sophisticated, most difficult and most expensive equipment in chip manufacturing. The lithography cost accounts for 1/3 of the total chip manufacturing cost, and the time consumed accounts for about 40% to 60% of the total wafer production time. And it also determines how small transistors on the chip can do. [19]

Lithography equipment is a projection exposure system, which is composed of ultraviolet light source, optical lens, alignment system and other components [20]. Its principle is to print the integrated circuit pattern (macroscopic) designed on the photomask plate (Mask) to the silicon substrate photosensitive material (microscopic) through light exposure to achieve pattern transfer. Among them, the light mask is equivalent to the camera negative, it is much larger than the chip, but also through photolithography, but usually made by maskless direct writing lithography.

The idea of lithography comes from printing technology, the difference is that printing records information through the change of light reflectivity of ink on paper, while lithography uses the photochemical reaction of light and photosensitive substances to achieve contrast change [21]. For example, the lithography machine is a giant SLR camera that can shrink the image on the photomask by millions of times and transfer it to the wafer through photochemical reaction. [22]

Lithography technology has experienced contact lithography, proximity lithography, all-silicon wafer scanning projection lithography, step-by-step repeated projection lithography to the current step-by-step scanning projection lithography [23], and the light source has undergone five wavelength iterations: from the initial high voltage discharge mercury lamp g-line (436 nm) to i-line (365 nm), to deep ultraviolet (DUV) excimer laser KrF (248 nm) and ArF (193 nm). And then to the state-of-the-art 13.5nm extreme UV (EUV). [24]

Why is the lithography machine so difficult to build? one challenge is to further improve the performance of the ultraviolet lithography machine. From the first generation lithography machine to the most advanced fifth generation lithography machine, the wavelength of the light source has been shortened from 436nm to 13.5nm. In addition to the difficulty in generating light sources, the attenuation of extreme ultraviolet light in beam transmission and the rough surface control of optical elements are great problems. Another challenge is that the unlimited increase of the two-dimensional density of the chip will inevitably encounter the quantum limit. The premise of the operation law of the electrons on the two lines of the chip is not to interfere with each other, but when the density of the silicon chip is reduced to less than 1nm on the physical scale, it will be disturbed and will no longer follow the classical electronics law, which is undoubtedly a great challenge. [25]

Not only that, under the pressure of yield, but also to ensure that the chip is cheap enough [26]. For example, an Intel CPU design document is generally above 10GB, while ASML's NXT:2050i can expose 295 300mm (12-inch) wafers per hour [24], and the Intel Ice Lake series CPU can cut out about 485 chips. In this case, the limit of exposure per hour can be 143,000 chips, so that the manufacturing capacity can reduce the cost of a single CPU to tens to thousands of dollars that the public can afford. [25]

In addition, the lithography system involves extremely detailed technologies, including:

Computational lithography: in actual production, it is difficult to make every lithography mode completely correct. Particle interference, refraction or other physical / chemical defects may occur in each lithography process. In order to obtain the exact pattern, it is necessary to combine the algorithm model with system and test wafer data, a process known as computational lithography; [27]

Focusing performance: the core part of the lithography machine is the lens, which is not an ordinary lens, but a huge lens up to 2m in diameter and 1m in diameter. The focusing performance of these lenses is the key to the imaging quality and product yield. With the continuous reduction of chip linewidth and the increasing application of secondary imaging (DP) lithography process, the focusing performance of lithography machine is more and more stringent. [28]

Process optimization: every step forward of the process node is accompanied by a large number of process optimization. for example, the process process starts from 20nm / 16nm / 14nm, and the design rule cycle is less than the resolution limit of the lithography machine. At this time, the lithography machine begins to adopt double or multiple exposure technology, light source mask collaborative optimization, negative development process and so on. Although immersion lithography supports five main technical nodes: 45nm / 40nm, 32 nm / 28nm, 20nm / 16nm / 14nm, 10nm and 7nm [29], but from 5nm to 3nm, 2.1nm and even 1nm, most of the cutting layers of fins and grids in the middle, rear and front segments are realized by EUV lithography. [30]

Summary of design rules for key lithography levels in 250nm to 1nm technology nodes [30] Lithography machines account for up to 20% of the semiconductor equipment value chain. At present, the major lithography companies in the industry are ASML (Asma), Nikon (Nikon) and Canon (Canon). [22]

On the market side, ASML, Nikon and Canon basically monopolize the market. In 2022, ASML shipments accounted for 82% of global shipments. Among them, ASML has a full range of lithography machines and is the only company in the world that can produce EUV lithography machines. At present, the minimum process reaches 3nm. Nikon focuses on DUV lithography machines and can also produce immersion lithography machines; Canon products are concentrated in the middle and low end. [31]

According to specific data, the total shipments of ASML, Nikon and Canon integrated circuit lithography machines in 2022 were 551 units, an increase of 15% compared with 478 units in 2021, an increase of 15% over the three high-end models of EUV, ArFi and ArF, and an increase of about 3% over the 152 units in 2021. In addition, the market share of EUV lithography machine ASML is 100%. The market share of ASML lithography machine is more than 95%, the market share of ASML of ArF lithography machine is more than 87%, the market share of KrF lithography machine ASML is more than 72%, and that of I-line lithography machine ASML is more than 23%. [32]

Shipments of TOP3 semiconductor lithography machines worldwide in 2022 [31] although the structure of the photoresist developer (or coating developer) equipment is not as complex as that of the lithography machine, it is also indispensable, it is a necessary equipment in the lithography process. [21]

For the lithography process, the thickness and uniformity of the photoresist coating on the wafer is very important, which directly affects the quality of the subsequent lithography process, thus affecting the performance, yield and reliability of the finished chip [33]. Therefore, how to apply photoresist is a subject, and the equipment responsible for applying photoresist is the photoresist development equipment.

Different light source for glue development equipment needs different, early low-end chip manufacturing often use glue development equipment (Off Line) alone, with 200mm (8 inches) and more large-scale production line put into application, modern semiconductor production, most glue development equipment and lithography system online production (In Line) [34], and it is with the lithography technology together, along with the lithography accuracy and increase the technical difficulty.

Glue development equipment with the lithography process iteration, technical difficulty improvement [35] glue development equipment is not a kind of equipment, but a kind of equipment, the lithography process includes HMDS (hexamethyldisilazane, tackifier) pretreatment, glue, pre-drying, exposure, post-drying, development and hard film, in which the main equipment used are glue coating, exposure and development equipment.

The structure of the glue-coated development equipment is complex and difficult to realize. Different manufacturers have their own understanding of the structure and form of the equipment, but they are basically composed of unit modules with similar functions, including dozens of functional module groups and supporting robots, hundreds of functional units and tens of thousands of parts. Such as box station unit CS, box station mechanical arm CSR, process robot arm PSR, glue coating unit COT, development unit DEV, heat drying / cooling OVEN unit, alignment unit CA, edge exposure unit WEE, etc., in addition, it also covers mechanical movement, temperature and humidity and internal environment control, system scheduling and control, chemical reaction and chemical control and other multi-disciplinary technologies. [21]

Lithography process flow chart [21] gelatinized developer accounts for about 5% of the semiconductor equipment value chain. Globally, companies such as Japan's TEL (Tokyo Electronics), Germany's SUSS (Hughes Micro Technology), Austria's EVG and domestic Shenyang Core Source all have mature plans, but TEL is basically in a monopoly position.

According to the data, TEL accounted for nearly 87% of the global market share of glue development equipment in 2019, while DNS (Deans) and other enterprises accounted for the remaining 13% market share. In 2019, TEL accounted for nearly 91% of the domestic market share of glue development equipment, DNS accounted for 5%, and domestic core micro products accounted for only 4%. [35]

2019 global and Chinese mainland glue development industry market situation [35] for domestic, the difficulty in selling glue development equipment lies in the downstream client process verification, because the glue development equipment and lithography machine are highly linked, therefore, the equipment manufacturers need in the normal production of downstream wafers, provide lithography machine, mask, testing equipment and procedures and other resources with, verification process is complex and lengthy, making it more difficult for manufacturers to apply. [36]

Etching machine and lithography machine are a pair of good friends, both of which determine the performance of the finished chip. For example, if you want to make 5nm chip, both lithography machine and etching machine must have 5nm process capability.

The principle of the lithography machine is that the mask circuit structure is copied to the wafer by light, and the etching machine microscopically carves grooves or contact holes on the wafer according to the structure copied by the lithography machine. For example, a lithography machine is like a craftsman marking a board, and an etching machine carving it according to the line on the board.

During the etching process, the wafer is baked and developed, and some of the resist is washed away, revealing the 3D pattern of the open channel. So far, the nanoscale chip has been composed of dozens or even hundreds of layers of structure. in this process, it is difficult to ensure the accurate formation of a complete and stable chip structure. avoid destroying the underlying structure of multi-layer microchips or creating cavities in the structure during etching. [27]

There are two kinds of etching: wet etching and dry etching. Wet etching uses chemical agents to clean the wafer, and dry etching is based on the pattern on the gas exposed wafer. Since the chip has been continuously miniaturized in the 1980s, the limitations of wet etching have become increasingly prominent, including not being able to use patterns below 3 microns, easily leading to etching pattern deformation, potential liquid toxicity and pollution, additional cleaning and drying steps, and so on. therefore, dry etching is gradually replaced in specific links, and now the two etching machines play an important role in their respective fields. [37]

Dry etching is divided into three methods: plasma etching, reactive ion etching and ion beam etching, which are applied in the process steps according to their different characteristics. Capacitive plasma etching and inductive plasma etching cover the main etching applications.

The manufacturing technology of etching machine is very difficult. In the case of plasma etching machine, inductively coupled plasma source is needed. In order to ensure plasma quality, ultra-high vacuum is needed.

Comparison of the three dry etching methods [37] etching machines account for up to 25% of the semiconductor equipment value chain, and the market growth rate is also very obvious. According to Transparency Market Research, the global market for semiconductor etching equipment is about $11.3 billion in 2022 and is expected to grow at a compound annual growth rate of 7.6% from 2023 to 2031 and reach $21.7 billion by 2031, driven by the growing importance of etching machines in the logic / storage field. [38]

Etching machines are monopolized by international giants. According to Gartner data, the top three in the global etching equipment industry in 2021 are Lam Research (Pan-Forest Semiconductor), Tokyo Electron (Tokyo Electronics) and Applied Materials (Applied Materials). Together, they occupy more than 90% of the market share, of which LAM has a market share of 46%, in a leading position. [17]

Competition pattern of global etching equipment in 2021 [17] most of the domestic etching machines are international brands, while foreign etching machines generally sell for millions of RMB each in China. The reason why they occupy such a dominant position is that as early as many years ago, they have begun to integrate and merge to seek monopoly premiums. For example, Applied Materials has merged with Tokyo Electronics, and Pan Lin Semiconductor has also sought to merge with Coley, trying to form a consortium. [39]

The situation of major foreign etching machine manufacturers [39] of course, in the field of etching machines, domestic etching machines cannot be achieved overnight. Etching machines require very high machining accuracy. For example, the processing scale of 16nm plasma etching machine is only 1/5000 of that of hair, and its requirements for machining accuracy and repeatability should reach 1/50000 of hair. This is not a problem in the field of etching machines alone, but is related to the development of domestic precision machine tools and other equipment [39]. At present, domestic medium and micro semiconductors, northern microelectronics, Jinsheng micro-nano technology and other companies have gradually realized the shipment of mainstream process equipment, constantly catching up with foreign giants.

Domestic etching machine main manufacturer situation [39] thin film deposition equipment thin film deposition (Thinfilm Deposition) is 1 μ m (micron) or less molecular / atomic material film covering the wafer surface technology, this layer of film can make the original non-conductive wafer with electrical conductivity.

For example, it is like using physical or chemical methods to turn electron gases into solids, spread them evenly from the air, and eventually form a film as thin as white paper, on which fine circuits are drawn. [40]

Thin film deposition can be divided into physical vapor deposition (Physical Vapor Deposition,PVD) and chemical vapor deposition (Chemical Vapor Deposition,CVD).

PVD thin films are formed by physical methods such as vacuum evaporation and sputtering. They are mainly used to deposit metal and metal compound films. They have been widely used in metal processes such as Ti, TiN, Al in integrated circuits, Fan-out, Ti / Cu-Copper Pillar, TiW / Au-Gold Bump in advanced packaging, Si-based, SiC-based IGBT and GCT devices in power semiconductors. Ti, Ni, NiV, Ag, Al, Cr, TiW, SiO2, ITO and other thin film processes in the field of MEMS.

CVD is a process of depositing thin films on the surface of the substrate by the reaction of mixed chemical gases. it is mainly used to deposit dielectric thin films. It has been widely used to prepare dielectric thin films such as SiO2, Si3N4, SiCN, SiON, phosphorosilicate glass, borosilicate glass, borosilicate glass, Si, PolySi, Ge, SiGe, GaAs, InP, GaN, SiC and W, Al, Cu, Ti, TiN, metal silicide and other metallized thin films. [41]

There are many types of thin film deposition technologies. PVD includes evaporation (evaporation), sputtering and ion beam process equipment, while CVD includes thermal chemical vapor deposition (APCVD, LPCVD, MOCVD), metal vapor deposition (MCVD), plasma vapor deposition (PECVD), atomic layer deposition (ALD), etc., according to the materials required for thin films, the production process equipment is also different, generally speaking:

During the PVD:150mm wafer period, it was mainly in the form of a single chip and single chamber, and then the sputtering equipment gradually replaced the vacuum evaporation equipment. with the development of IC technology, more technologies were introduced into the magnetron sputtering equipment, and the radio frequency PVD equipment and ionization PVD equipment were developed synchronously.

CVD: in the micron era, atmospheric pressure chemical vapor deposition equipment (Atmospheric Pressure CVD,APCVD) is mostly used, while the mainstream equipment of submicron technology is low pressure chemical vapor deposition equipment (Low Pressure CVD,LPCVD). Plasma enhanced chemical vapor deposition equipment (Plasma Enhanced CVD,PECVD) plays a major role after 90nm, and the demand for atomic layer deposition (Atomic Layer Deposition,ALD) is increasing after 65nm. [41]

Main film deposition methods [42] Film deposition accounts for a high proportion of value in manufacturing equipment, of which CVD is about 17% (ALD is 4%) and PVD is about 5%. At the same time, the film deposition equipment industry is still a high monopoly industry.

In the global market, CVD field American Applied Materials (AMAT), Pan Lin Semiconductor (Lam Research) and Tokyo Electronics (TEL) together occupy 70% of the global market share, of which Tokyo Electronics (TEL) and ASM (ASM) occupy nearly 50% of the global market share of ALD equipment necessary for advanced processes. The field of PVD is mainly monopolized by American Applied Materials (AMAT), Swiss Evatec and Japanese Ulvac, of which applied materials account for nearly 85%. [42]

CVD, PVD, ALD global market pattern [41] domestic competition in the field of thin film deposition is different from foreign giants, foreign giants are rich in products and a wide range of technology coverage, while the domestic is mainly differentiated competition in the field of subdivision, such as Tuojing Technology, the main product of Micro and Micro is CVD, the main product of North Huachuang is PVD, the main product of microconductor is ALD, and the main products of Shengmei Semiconductor are electroplating products. [41]

In the process of manufacturing heat treatment equipment chips, there are many high temperature heat treatment steps involving 700 ℃ ~ 1200 ℃. These processes are usually carried out in high temperature furnaces, including oxidation, diffusion, annealing and other main processes. [43]

The chip manufacturing process usually starts with the oxidation process, which is also one of the most important heating processes. When the wafer is exposed to the atmosphere, the substance forms an oxide film with oxygen, just as iron oxidizes and rusts when exposed to the atmosphere. Therefore, the function of oxidation is to form a protective film on the surface of the wafer, protect the wafer from chemical impurities, prevent leakage current from entering the circuit, prevent diffusion during ion implantation, and prevent wafer slippage during etching. [44]

The oxidation process includes thermal oxidation (Thermal Oxidation), plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition,PECVD) and electrochemical anodization, among which thermal oxidation is the most commonly used method. According to the gas used in oxidation reaction, thermal oxidation can be divided into dry oxidation (Dry Oxidation) and wet oxidation (Wet Oxidation). [45]

Classification and characteristics of oxidation process, mapping (hard science and technology of fruit shell)

Reference materials, Samsung [45]

The main function of the diffusion process is to doping the wafers at high temperature, but this mainly existed in the early process before the 1970s, when the chip pattern feature size was mostly of the order of 10 μ m, but now in advanced chip production, diffusion doping technology is rarely used except in specific cases.

The annealing process is to put the silicon wafer in a high temperature environment for a period of time to change its surface or internal microstructure, which is usually combined with ion implantation, thin film deposition, metal silicide formation and so on.

The basic equipment for oxidation, diffusion, annealing and other heating processes are horizontal furnace, vertical furnace and rapid heating furnace (RTP).

Heat treatment equipment accounts for about 3% of the semiconductor equipment value chain, while the global market for heat treatment equipment is monopolized by oligopolies. The combined market share of American Applied Materials (Applied Materials), Tokyo Electronics (Tokyo Electrion) and Japanese peer International Electric (Kokusai Electric) is more than 80%, while domestic non-laser annealing equipment Yitang Semiconductor has 5% market share, and North Huachuang has 0.2% market share. [46]

Competition pattern of global thermal process equipment in 2018 [47] Ion implantation equipment to turn non-conductive pure silicon into semiconductors, it is necessary to add substances such as nitrogen and phosphorus to silicon to form PN junctions (PN junction, a semiconductor structure), and then create transistors to form a variety of semiconductor devices. Among them, the process of artificially adding elements to silicon is Doping.

Doping process is very important, only after doping, the wafer will have electrical conductivity, can be called semiconductors. Not only that, doping also determines what functions or properties semiconductors can achieve. By changing the electrical properties of semiconductors, such as conductivity, carrier type and concentration, band structure and so on, people can control semiconductors freely.

For example, N-type semiconductors can be obtained by adding pentavalent elements phosphorus or arsenic to silicon materials, and P-type semiconductors can be obtained by doping trivalent elements such as boron.

In chip manufacturing, impurities can be added in the early stage of single crystal growth, such as specific donor or acceptor elements in the CVD growth process, so that some atoms in the film can be replaced by corresponding elements.

For the wafers that have been manufactured, thermal diffusion (Diffusion) and ion implantation (Implant) are mainly used for doping. It has been mentioned in the heat treatment equipment of this paper that the thermal diffusion process is basically replaced by ion implantation because it is difficult to achieve selective diffusion.

The principle of ion implantation is very simple and easy to understand, that is, the impurity ions are accelerated by a high energy electric field, which directly bombards the surface of the semiconductor and finally squeezes into the crystal. The ion implantation equipment is like a sharpshooter, shooting various elements accurately and evenly into the inside of the wafer, and this is the technical difficulty of the ion implantation equipment, that is, to accurately control the doping dose and depth (particle range) without damaging the microstructure.

According to the energy range and beam current of ion beam, ion implantation equipment can be divided into low energy, medium energy, high energy, megavolt, small beam current, medium beam current and high beam current. However, in practical applications, more than 60% use low-energy large beam ion implantation equipment to manufacture logic chips, DRAM, 3D NAND and CIS chips, 18% use high-energy ion implantation equipment for manufacturing power devices, IGBT, 5G radio frequency, CIS, etc., and 20% use medium beam ion implantation equipment. [48]

Classification and description of ion implantation equipment, mapping? fruit shell hard science and technology

Reference material Leopard [49]

Ion implantation equipment accounts for a small proportion of the value of manufacturing equipment, about 3% of the global market for ion implantation equipment is about $2.4 billion to $2.6 billion, and it is long-term estimated that the market will grow to $4.2 billion in 2030. [50]

There are only nine global ion implantation equipment vendors (including semiconductors, photovoltaics and panels). The semiconductor field is monopolized by AMAT and Axcelis, which together have a global market share of nearly 88 per cent. [49]

Global market situation of ion implantation equipment, mapping? fruit shell hard science and technology

Reference material: bank of China Securities [50]

In the domestic market, only Kaishitong and China Science and Technology can produce ion implantation machines. in addition, suppliers such as American Applied Materials Corporation (AMAT), American Asheri Technology (Axcelis), American AIBT, and Japan's Sumitomo have taken the market share of most domestic fab factories, and the localization rate of some representative wafer factories is only 1% to 3%. [50]

With the continuous reduction of the manufacturing process of CMP equipment, the scale of measuring transistors is getting smaller and smaller, so the requirement of wafer flatness becomes higher and higher. In this case, chemical mechanical flattening (Chemical Mechanical Polishing,CMP) process is needed to achieve wafer surface planarization.

As the name implies, CMP is a collaborative chemical etching and mechanical grinding process, different from traditional pure mechanical and pure chemistry, CMP can effectively avoid pure mechanical surface damage and pure chemical polishing speed, surface smoothness and poor polishing consistency and other shortcomings [51], this process will be repeatedly used in chip manufacturing, including before lithography, after film deposition or in advanced packaging.

It can be said that the smaller the process node, the more CMP is required. For example, from 180nm to 14nm CMP CMP process, the number of steps will be increased from 10 to more than 20, while the number of CMP steps in the CMP process will even exceed 30. [52]

CMP equipment is divided into metal and non-metal machines, non-metal machines mainly include intermetallic dielectric planarization (IMD CMP), interlayer dielectric planarization (ILD CMP) and shallow groove isolation planarization (STI CMP), while metal machines mainly include copper, tungsten, aluminum and so on.

The CMP equipment consists of three modules: polishing, cleaning and transmission. in the process of operation, the polishing head presses the wafer surface to be polished against the rough polishing pad, and realizes global planarization with the help of polishing fluid corrosion, particle friction, polishing pad friction, etc., so the polishing liquid and polishing pad are the two major consumables in the process. [53]

CMP technology is a new process that began to be applied on a large scale from the 0.35 μ m process node. once upon a time, it was just an ugly duckling.

In the early 1990s, due to the increasingly strong pursuit of flatness in lithography, CMP came into being and was used for the leveling of back-end (BEOL) metal connection interlayer medium. at this time, this technology has not attracted the attention of the industry. In the mid-1990s, during the 0.35 μ m process, shallow groove isolation polishing (STI CMP) replaced LOCOS, and tungsten polishing (W CMP) replaced reverse etching (etch back). At the beginning of the 21st century, the emergence of copper polishing (Cu CMP) made the 0.13 μ m back-end copper process a reality, and then Cu CMP has been used all the time to 90/65/45/32/28/22nm. In recent years, with the continuous reduction of process nodes and higher requirements for CMP, new CMP applications emerge in endlessly. [54]

CMP technology development history, reference materials: "Nano-scale Circuit Manufacturing process" [54], at present, the most advanced 5/3nm process is still using CMP technology, while the 12-inch wafer is still the size standard adopted by the most advanced process, so there is no technology iteration cycle for CMP equipment for a long time in the future, but the core module technology and control system in the equipment will continue to upgrade. [55]

CMP equipment accounts for about 3% of the semiconductor equipment value chain, while American Applied Materials and Japan Ehara together occupy more than 90% of the global market share of CMP equipment. CMP equipment of the two companies have reached the level of 5nm process technology. Most of the high-end CMP equipment in China is also provided by American Applied Materials and Ebara of Japan. [55]

Global market situation of CMP equipment, tabulation (fruit shell hard technology)

Reference materials: national Gold Securities [56]

Domestic aspect, at present, mainly for low-end products, 12-inch high-end CMP equipment is in the product verification stage, among which, Huahai Qingke CMP equipment has officially entered the integrated circuit production line, Shengmei Semiconductor CMP equipment is mainly used for back-segment packaging 65~45nm copper interconnection process, and Hangzhou Zhongde Company, established by 45 CMP technology experts of China Electric Power Division, is also gradually moving towards a new step. [51]

Cleaning technology in semiconductor cleaning equipment refers to the process of removing pollutants and oxides by physical or chemical methods before semiconductor manufacturing processes such as oxidation, lithography, epitaxy, diffusion and lead evaporation.

Chips have a serious penchant for cleanliness, which is due to electrical failures caused by defects caused by contamination, with a proportion as high as 80% [57]. If there are pollutants in the wafer manufacturing process that can not be completely removed, the wafer yield will be affected, and a whole wafer or even a batch of wafers will be scrapped.

Cleaning can run through the whole industry chain of chip manufacturing, accounting for more than 30% of the semiconductor manufacturing process. SEMI data show that there are about 100 steps in the cleaning process in the 80nm~60nm process, while there are more than 200 steps in the 20nm~10nm process [58]. It is also the process with the largest number of repetitions, including three types of processes:

In the wafer manufacturing process: clean the polished wafer, ensure the surface smoothness and performance, and improve the yield of the follow-up process.

In the wafer manufacturing process: cleaning before and after lithography, etching, deposition, ion implantation, de-gluing and other key processes to reduce the defect rate.

In the process of chip packaging: TSV cleaning, UBM / RDL cleaning, bonding cleaning and so on are carried out according to the packaging process.

According to the different cleaning media, semiconductor cleaning is divided into wet cleaning and dry cleaning. The former uses deionized water and chemical solvents, assisted by ultrasonic, heating, vacuum and other physical methods to clean the wafer surface. The latter does not use chemical solvent cleaning technology. Among them, 90% of the cleaning steps use wet cleaning technology, but both are indispensable and each plays a different role.

Cleaning equipment accounts for about 6% of the semiconductor equipment value chain. From the current situation of international and domestic cleaning equipment, the Matthew effect is significant. The global semiconductor cleaning equipment market shows a highly concentrated trend. According to Gartner data, DNS (Deans), TEL (Tokyo Electronics), SEMES and LAM (Pan Lin Semiconductor) accounted for 45.1%, 25.3%, 14.8% and 12.5% of the global semiconductor cleaning equipment market share in 2020, respectively. [59]

There are very few domestic enterprises that can provide semiconductor cleaning equipment, mainly including Shengmei Semiconductor, North Huachuang, Core Source Micro and to Pure Technology. At present, four domestic enterprises have 130nm~28nm mainstream process cleaning equipment technology, among which Shengmei Semiconductor has been studying 7/5nm cleaning equipment technology.

Compared with other types of semiconductor equipment, the domestic growth rate of cleaning equipment is obvious, and the domestic production rate has increased from 15% in 2015 to 20% in 2020 [60]. The domestic deficiency mainly lies in the advanced wet cleaning equipment. Four companies, DNS (Deans), TEL (Tokyo Electronics), LAM (Pan-Forest Semiconductor) and SEMES, account for 90% of the market share of monolithic cleaning equipment.

The production process of integrated circuit of testing and measuring equipment is complex, there are hundreds of processes only in the previous process, quantitative change causes qualitative change, and the defects of each process will be magnified to several times or even dozens of times with the passage of time, so only by ensuring that there are no defects in each process can the performance of the final product be guaranteed.

In other words, every step in production, it is necessary to check the production situation. Just like the medical equipment such as CT, color ultrasound, biochemical analyzer and so on, these tools for the "physical examination" of the pre-chip process are the testing and measuring equipment.

Errors of several nanometers, size changes, particles or image errors will cause the chip to not work properly. If the yield of each process in the previous process is lost by 0.1%, the final yield will be reduced to 36.8% [61]. Testing and measuring equipment, as the two major equipment of front inspection, can effectively control the manufacturing process and increase the output.

Testing equipment: used to detect wafer surface defects (including foreign body defects, bubble defects, particle defects, etc.), divided into open / dark field optical image defect detection equipment, non-pattern surface inspection equipment, macroscopic defect detection equipment, etc.

Measuring equipment: used to measure transparent / opaque film thickness, film stress, doping concentration, key size, lithography registration accuracy and other indicators, the corresponding equipment is divided into ellipsometer, four probes, atomic force microscope, CD-SEM, OCD-SEM, thin film measurement, etc. [62]

The research and development of semiconductor testing and measurement equipment is difficult and expensive, but the market space is not as large as the middle and lower reaches of integrated circuits or chips, and the growth rate is relatively stable. However, it accounts for about 12% of the value of manufacturing equipment, which is relatively large.

According to the data, the global semiconductor measurement equipment will increase from US $7.3 billion in 2021 to US $13.3 billion in 2031, with a compound annual growth rate of 6.2%. At the same time, the global concentration of this field is extremely high, with KLA, Applied Materials and Hitachi accounting for 50.8%, 11.5% and 8.9% of the global market, respectively. [63]

The localization rate of semiconductor testing and measurement equipment in China is very low, and the localization rate of semiconductor testing and measurement equipment in China is about 2% in 2020. Klei Semiconductor, Applied Materials and Hitachi occupy 54.8%, 9.0% and 7.1% of China's testing and measurement equipment market, respectively. While China's overall market accounts for about 27.4% of the global market, it is estimated that the market scale of China's testing and measuring equipment will reach 32.6 billion yuan in 2023. [64] [65]

Global market pattern of semiconductor testing and measurement equipment in 2020 [62] 3. Previous technology: material consumption is the cornerstone of chip production. From ancient times to the present, the development of history is closely related to materials. Each era is marked by the corresponding material names, such as the Stone Age, the Pottery Age, the Bronze Age, the Iron Age and the porcelain Age [66]. Almost all of the 35 techniques of neck jam are related to materials. [67]

The semiconductor industry is undoubtedly an industry that plays with materials, involving a large variety of materials and demand, and these materials will also be a crucial part of pre-processing.

Semiconductor materials are divided into wafer manufacturing materials and packaging materials. The materials consumed in pre-processing mainly include silicon materials, targets, CMP polishing materials, photoresist, wet electronic chemicals, electronic special gases, photomask and so on. [9]

According to SEMI data, the market size of semiconductor materials in the global industry decreased first and then increased from 2015 to 2021. In 2021, the global semiconductor materials market accounted for about 11.56% of the total size of the global semiconductor industry. The global semiconductor materials market sales in 2022 reached US $72.7 billion, an increase of 8.9% compared with US $66.8 billion in 2021, of which wafer manufacturing materials and packaging materials accounted for US $44.7 billion and US $28 billion respectively, accounting for 61.5% and 38.5% of the global material market sales, respectively. In addition, sales of Chinese mainland materials in 2022 were US $12.97 billion, accounting for about 17.8% of the global market. [68]

The global classification scale of semiconductor materials accounts for the proportion of the global semiconductor materials in 2021. [9] Silicon consumption in the semiconductor industry is very large. Statistics show that from 2015 to 2021, the scale of the domestic semiconductor silicon market increased from 10.16 billion yuan to 25.05 billion yuan, with a compound growth rate of 16.2%. At present, the technical level of domestic semiconductor silicon production enterprises has made remarkable progress, and can maintain a high proportion in the domestic market. [9]

China's silicon market scale bar chart from 2015 to 2021 [9] the price of semiconductor silicon is linked to the prosperity of the semiconductor wafer industry. According to SEMI data, the price of silicon has increased from US $0.67 per square inch in 2016 to US $0.98 per square inch in 2021. [9]

Global average selling price of semiconductor silicon wafers [9] the mask mask is an important material in the lithography process, which is used to selectively block exposure, irradiation or material penetration. To put it simply, a mask is a negative in the process of lithography, which can copy the above pattern to the wafer. According to the purpose, the mask plate is divided into main mask, intermediate mask, working mask, phase shift mask and so on.

Nowadays, there are often erroneous writing methods in the media and even official publications, such as "mask" or "mask". In fact, its standard writing is the "mold" of "masking mold" and should not be written as "film". At the same time, the "version" of the mask is a "published version", not a "plate" of "plate". [26]

The mask itself is also derived from the lithography process, but unlike the chip, the mask itself is much larger than the chip, so it usually does not use the difficult and expensive lithography technology such as DUV and EUV lithography, but uses optical pattern generator, laser pattern generator and electron beam pattern generator for mask pattern exposure. [26]

Masks account for about 12% of the global semiconductor material market, and it is estimated that the global mask market will be US $7.716 billion in 2021, of which 24% are for display panels and 65% for integrated circuits. [69]

In terms of flat panel display, Photronics, SKE, HOYA, LG-IT, Qingyi Optoelectronics and Lowe Optoelectronics accounted for 24%, 22%, 21%, 21%, 7% and 5% of the global market share in 2020, respectively. In terms of integrated circuits, 65% of the global market is produced by semiconductor manufacturers (such as Intel, Samsung, etc.), and third-party companies Photronics (Fox), Toppan (letterpress) and DNP (Greater Japan Printing) account for 11%, 10% and 8% of the global market share in 2020, respectively. [70]

Global template market in 2020, tabulation (fruit shell hard technology)

Reference materials: Anxin Securities [70]

Photoresist, also known as "photoresist", is the carrier of photoetching imaging, which can use photochemical reaction to convert the diffracted and filtered light information in the lithography system into chemical energy. thus the fine pattern is transferred from the mask to the substrate to be processed. It is widely used in the fabrication of micro-pattern circuits in optoelectronic information industry, and it is the key material of micro-machining technology.

In a word, photoresist is the most important consumable material in lithography process, and its performance determines the precision and yield of finished products.

In terms of dosage, the solvent (mainly propylene glycol methyl ether acetate, referred to as PMA) is the largest material, with a content of up to 90%, but it is not prominent in cost and does not play a key role; as the core part of photochemical reaction, the dosage of photoinitiator is only about 1% 6%; the amount of resin in different photoresist products varies greatly. [71]

In terms of cost, in the field of semiconductor photoresist, the more advanced the process, the higher the resin cost: take KrF (krypton fluoride) photoresist as an example, the resin cost is about 75%, the photosensitive agent is about 23%, and the solvent is about 2%. [72]

According to the exposure wavelength, semiconductor photoresist can be further divided into ordinary wide photoresist, g line (436nm), I line (365nm), KrF (248nm), ArF (193nm), and the most advanced EUV (

Welcome to subscribe "Shulou Technology Information " to get latest news, interesting things and hot topics in the IT industry, and controls the hottest and latest Internet news, technology news and IT industry trends.