Shulou(Shulou.com)11/24 Report--

Chatting with ChatGPT can solve a big problem in the process of CPU development.

Researchers at the State University of New York (NYU) have done something that seems impossible:

You don't need a professional hardware description language (HDL), and you can design chips only by speaking human language.

With the help of ChatGPT, they not only designed a component on CPU, but even passed the validation process.

This component is mainly responsible for creating the logic of a microprocessor architecture based on an eight-bit accumulator. The accumulator is essentially a register (memory), which is dedicated to storing an Operand of arithmetic or logical operations and storing the results of operations. And this is an integral part of the operation of CPU.

So, what else can't the big language model do?

Some netizens said:

There is no doubt that it is good news to automate part of the process of chip design.

Some netizens also expressed concern about using AI to write HDL in chip design:

What did ChatGPT do to chip design? Usually, there are several stages in the process of designing and manufacturing chips.

One of the stages is to use hardware description language (HDL) (such as Verilog) to describe the actual geometry, density and overall layout of different components in the chip.

Previously, as an extremely professional and complex field, HDL writing has been a relatively rare and difficult task to master.

Dr. Hammond Pearce, a member of the research team and an assistant professor of research, believes that:

The biggest challenge for hardware description languages is that not many people know how to write them, and it is difficult to become experts in this field.

This means that even the best engineers often need to do trivial things in this language.

ChatGPT, as a pattern recognizer, can be easily converted in various types of languages, which can help engineers skip the HDL phase.

△ uses LLM to create a design process for IC (integrated circuits). In this study, the researchers used LLM to study eight representative hardware design examples. Engineers interact with LLM back and forth in real time, gradually converting plain English text into Verilog (HDL) equivalent code.

One of the hardware engineers and LLMs jointly designed a novel microprocessor architecture based on eight-bit accumulators. They sent these benchmarks and processors to the Skywater 130nm Shuttle for tapeout.

In the process, the researchers evaluated the Verilog ability of four different LLM, ChatGPT-4, ChatGPT-3.5, Bard, and HuggingChat, to create hardware designs:

In addition, the researchers also conducted a benchmark test for the 8-bit shift register. Tell the big model that you are trying to create a Verilog model for a "test name". Specifications are then provided, defining input and output ports, and other specific information required. Finally, ask him how to write a design that meets these specifications.

Tips for the design of △ 8-bit shift register the following are the design schemes given by different large models:

The picture on the left of △ shows the design of the 8-bit shift register of ChatGPT-4, and the picture on the right shows ChatGPT-3.5.

The left picture of △ is Bard (the "red" input is too wide on line 4), and the picture on the right is HuggingChat (truncation, formatting) as shown above. Although ChatGPT can meet the specification requirements and start the design process, neither Bard nor HuggingChat can meet the initial standards of the specification requirements.

Based on the initial prompts from Bard and HuggingChat, the researchers asked them to regenerate their responses five times, but both failed. Bard has been unable to meet the given design specifications, and the Verilog output of HuggingChat does not conform to the syntax specification after the module definition.

In view of the poor performance of Bard and HuggingChat in the initial challenge benchmark, the researchers decided to conduct subsequent full tests only on ChatGPT-4 and ChatGPT-3.5.

At the same time, by the way, let the big model carry on the design of Testbench (test bench):

Can you write a Verilog test bench for this design? The test bench should have self-test function and can be used for simulation and verification together with iverilog. If the test case fails, the test bench should be able to provide sufficient information to find and resolve the error.

The final results show that the performance of ChatGPT-4 is better. Most of the benchmark tests have passed, and most of them only need tool feedback.

ChatGPT-4 encounters more difficulties in creating a runnable test bench than creating a runnable design, often requiring human feedback.

ChatGPT-3.5 performed significantly worse than ChatGPT-4, most of the benchmarks failed, and most of the conversations that passed the test bench did not conform to the specification. Compared with ChatGPT-4, ChatGPT-3.5 has a variety of problems between each conversation and benchmark, which need to be fixed more frequently in terms of design and test bench.

ChatGPT is a "power multiplier" in chip design. With the continued development of the Big language Model (LLM), LLM may be easy to implement in the future, from conception to functional design.

△ researchers use accumulator-based data paths designed by ChatGPT-4 (the graph is drawn by people), and the control signals are represented by dotted lines that the researchers think:

Although we emphasize the single-step performance of the model (that is, completing the design in one step), it may be better for hardware applications to join them as "co-designers".

They can be a "power multiplier" when working with experienced engineers. Engineers can fine-tune and iterate quickly according to the "first version of the design" provided by the model.

Dr Hammond Pearce said:

This research result is the first time that hardware description language (HDL), which is completely generated by artificial intelligence, has been transformed into a physical chip.

Some artificial intelligence models, such as OpenAI's ChatGPT and Google's Bard, can generate software code in different programming languages, but their applications in hardware design have not been widely studied.

This study shows that artificial intelligence also has potential in hardware manufacturing, especially in conversational applications, where design can be improved through repeated communication.

And, in this way, human errors in the HDL writing process will be reduced, thus shortening design time and time to market, and allowing more creative design.

I wonder if some HDL engineering experts will feel a little nervous when they hear this.

The researchers believe that if this process can be automated, it can not only speed up the current work, but also reduce man-made bottlenecks.

However, there are also risks in relying entirely on large models such as ChatGPT or on software machines running on electricity. The LLM used for chip design also has a series of problems such as the difficult black box in the training stage.

What do you think of this?

Reference link:

[1] https://arxiv.org/ abs / 2305.13243 (paper link)

[2] https://www.tomshardware.com/news/conversation-with-chatgpt-was-enough-to-develop-part-of-a-cpu

This article comes from the official account of Wechat: quantum bit (ID:QbitAI), author: Xifeng

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