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Tokyo Electronics announces the development of a new etching technology with 400 layers of stacked 3D NAND flash memory approaching

2025-04-06 Update From: SLTechnology News&Howtos shulou NAV: SLTechnology News&Howtos > IT Information >

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Thanks to CTOnews.com netizen Xiao Zhan for the clue delivery! CTOnews.com, June 12, Tokyo Electronics (TEL) recently announced that it has developed a through-hole etching technology for memory chips, which can be used to make 3D NAND flash memory chips stacked with more than 400 layers. TEL said the technology brought the application of electroetching to a low temperature range for the first time and creatively invented a system with extremely high etching rates.

▲ Tokyo Electronics specifically, this new technology can etch at a depth of 10 microns in as little as 33 minutes with a high aspect ratio (CTOnews.com Note: aspect ratio is the ratio of the depth to width of the pattern formed on the wafer), which takes much less time than previous technologies. According to TEL, the application of the technology not only helps to produce higher-capacity 3D NAND, but also reduces the risk to global warming caused by the production process by 84 per cent.

▲ Touyuan Tokyo Electronics TEL predicts that the R & D team will release the latest results and reports at the 2023 VLSI Technology and Technology Symposium to be held in Kyoto, Japan, from June 11 to 16.

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