Shulou(Shulou.com)11/24 Report--

Thanks to CTOnews.com netizens Wu Yanzu in South China for the delivery of clues! CTOnews.com, June 5 (Xinhua)-- Intel will present three highly anticipated papers at next week's VLSI seminar, one of which is the development of power supply technology on the back of the upcoming PowerVia chip.

Intel will next launch two key technologies: full-loop gate transistor RibbonFET technology and PowerVia. This will serve as a combination of Intel's punch on the lithography industry, and Intel believes it will be the key to helping them regain their leadership in wafer factories.

As Intel's industry-leading back power solution, PowerVia will be launched on Intel 20A process nodes in the first half of 2024. By moving the power cord to the back of the wafer, PowerVia solves the increasingly serious problem of interconnection bottleneck in chip unit area miniaturization.

According to reports, Intel announced that it is the first in the industry to implement back power supply (backside power delivery) technology on product-level test chips to meet the performance requirements of the next computing era.

Simply put, the PowerVia can make better use of the back of the chip and will make its debut at the Intel 20A process node in the first half of 2024 (the first product is Arrow Lake). It can solve the increasingly serious interconnection bottleneck in the process of chip miniaturization by moving the power wiring to the back of the wafer.

"PowerVia is an important milestone in our active 'four-year, five-node' strategy and on our path to achieving trillions of transistors in packaging by 2030. The use of test process nodes and subsequent test chips enables us to reduce the risk of back power supply our leading process nodes, putting Intel ahead of its competitors in bringing back power transmission to market."

-Ben Sell, Vice President of Technology Development, Intel

Intel said it had separated PowerVia development from transistor development to ensure that it was ready for Intel 20A and 18A process nodes.

Intel tested on its own test node and finally proved to be able to use chip resources very effectively, with a unit utilization rate of more than 90%, and is expected to reduce costs and make chip designers thermal. Be able to achieve higher performance and efficiency in its products.

On the technical side, tests show that the voltage drop of Intel platform has been improved by more than 30%, and the profit of E-core frequency is as high as 6%. Moreover, Intel has achieved higher power density in PowerVia test chips in line with the higher power density expected by logical scaling.

Intel will unveil more details in the form of two papers at the VLSI seminar in Kyoto, Japan, from June 11 to 16, when CTOnews.com will bring you more reports.

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