Shulou(Shulou.com)11/24 Report--

CTOnews.com news on June 4, David McAfee, vice president and general manager of customer channel business of AMD, talked about the mixed CPU design scheme of "large and small cores" during Computex 2023, saying that he would avoid the embarrassment of Intel blocking AVX-512 instruction set.

In an interview, Tu Yuan AMDMcAfee emphasized the view of AMD CTO Mark Papermaster that in the future AMD processors will mix high-performance core and high-efficiency core to navigate various scenarios and accelerate user experience.

AMD will be equipped with a Zen 4c efficiency core on the upcoming EPYC Bergamo chip; the current Ryzen 7040 notebook chip also uses a hybrid design, but there are no two different types of CPU cores.

The media asked: "conceptually, is the efficiency core more suitable for AI than a dedicated chip (AI engine)?"

CTOnews.com translator McAfee replied as follows: "strictly speaking, the AI engine is better at handling AI-related tasks than all general-purpose CPU cores (including efficiency cores, naturally)."

As for the problem with Intel's AVX-512 instruction set, the performance core supports it while the efficiency core does not, so Intel directly blocked the AVX512 instruction set on the 12th-generation Kerry processor.

Of course, the AVX512 instruction set can improve floating-point performance several times, but the problem is that after it is enabled, it often leads to a significant reduction in CPU frequency due to high power consumption.

Linus Torvalds, the father of Linux, once spurted this problem, saying, for example, that the extremely strong Wmuri 2104 processor could reach 3.2GHz under non-AVX and only 2.4GHz at AVXmure 512.

McAfee's views on "large and small cores" hybrid design are as follows:

In my opinion, different ways of supporting ISA, adjusting IPC, etc., are not necessarily the right way to harness the core of performance and efficiency.

I think there will be great challenges in the actual implementation process. We have studied the different core configuration options and found that the implementation is too complex, and this is not the approach we are currently taking.

From the point of view of application, we hope to promote the design of large and small cores in a more homogeneous way, and fully consider the positioning of different cores, so as to give full play to its advantages. These improvements can be confirmed in our future products.

We will first and foremost ensure that ISA and workloads are consistent across all cores, which will bring huge benefits.

Today, with the development of the desktop Ryzen processor, the scheduling of the Windows system has been "familiar" to identify which processes need the core to speed up priority processing and which can be delayed later, and then direct tasks to different cores according to CPU performance rankings and threads.

AMD has been in use for a long time, and it is a very mature technology that leads to a more consistent running mechanism for kernel functions.

I think this is a time-tested and more realistic way to help us design a variety of different core combinations. Relatively speaking, Intel's existing methods become too complex in practice, and AMD will take a different path from Intel's "big and small cores".

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