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The second generation of domestic "Xiangshan" RISC-V open source processor plans to stream in June: based on SMIC 14nm process, the performance is superior to Arm A76.

2025-01-18 Update From: SLTechnology News&Howtos shulou NAV: SLTechnology News&Howtos > IT Information >

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CTOnews.com May 28 news, the Chinese Academy of Engineering academician Ni Guangnan once pointed out that the current CPU market is mainly monopolized by x86 and ARM architecture, and China wants to break this situation and achieve independent control, open source RISC-V architecture will be a great opportunity and development direction.

In yesterday's "RISC-V open source processor chip ecological development forum", the second generation of "Xiangshan" (Nanhu architecture) open source high-performance RISC-V core was officially released. According to reports, "Xiangshan" started engineering optimization in June 2022, completed development in September of the same year, and plans to stream films in June 2023. The performance of the Cortex-A76 released by ARM in 2018 is better than that of Cortex-A76 released in 2018, with a score of 20 points for the main frequency of 2GHz 14 nm SPEC 2006.

Xiangshan uses lakes to name each generation of architecture-the first generation architecture is Yanqi Lake, the second generation architecture is Nanhu, and the third generation architecture is Kunming Lake. Xiangshan open source community said that the first generation of "Yanqi Lake" architecture has been successfully filmed, measured to achieve the expected performance, the second generation of "South Lake" architecture is in continuous iterative optimization.

On August 24 last year, a joint R & D team was formed by the Institute of Computing of the Chinese Academy of Sciences, Beijing Open Source Chip Research Institute, Tencent, Ali, ZTE, China Kechuangda, Yi Siwei, and Maneng. Carry out the joint development of the third generation Xiangshan (Kunming Lake architecture).

Officials also revealed that a number of enterprises in China are developing high-end chips based on "Xiangshan", such as AI chips, server chips and GPU, which are expected to make a collective breakthrough in 2025. Bao Yungang said that at that time, Chinese enterprises are expected to take the lead in the new global RISC-V ecology, open up the domestic and foreign cycles in the chip field, and achieve self-reliance in China's high-end processor chip industry.

According to CTOnews.com query, Xiangshan is an open source RISC-V processor core, which is based on Chisel hardware design language and supports RV64GC instruction set.

"Nanhu" is manufactured by SMIC 14nm technology, with a target frequency of 2GHz / GHz CPU score of 10 points / GHz, supporting dual-channel DDR memory and more functions such as PCIe, USB, HDMI and so on.

According to reports, "Xiangshan" is currently the highest-performance open source RISC-V processor core in the world. At present, it has determined the development goals of "Xiangshan" classic core and "Xiangshan" high-performance core.

The classic core is based on the second-generation "Xiangshan" engineering optimization, calibrating ARM A76, providing CPU IP cores for industrial control, automotive, communications and other pan-industrial fields, while the high-performance core is based on the third-generation "Xiangshan" (Kunming Lake) performance improvement, calibrating ARM N2, providing high-performance CPU IP cores for data centers, computing facilities and other fields.

One of the important decisions in the development of "Xiangshan" processor core is to choose the agile design language Chisel, because the development efficiency is much higher than that of Verilog and achieves the same function, and the code amount of Chisel is only 1 / 5 of Verilog.

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