Shulou(Shulou.com)11/24 Report--

Thanks to CTOnews.com netizens Wu Yanzu in South China for the delivery of clues! CTOnews.com May 23, Intel Programmable Solutions Division announced today that Intel Agilex 7 with R-Tile chipsets is being shipped in bulk. This will bring customers the first FPGA with PCIe 5.0 and CXL capabilities, and the only FPGA product with hard intellectual property to support these interfaces.

"customers need cutting-edge technology to provide scalability and customization, not only to effectively manage current workloads, but also to adjust capabilities and capabilities as demand evolves. Our Agilex products provide customers with the speed, power and functional innovation they need, while providing flexibility and flexibility for the future. For example, customers are using R-Tile and PCIe Generation 5 and CXL to accelerate software and data analysis, reducing processing time from hours to minutes, "said Shannon Poulin, vice president and general manager of Intel's Programmable Solutions Group.

Faced with time, budget, and power constraints, organizations in a variety of industries, including data centers, telecommunications, and financial services, use FPGA as a flexible, programmable, and efficient solution. With Agilex 7 and R-Tile, customers can seamlessly connect their FPGA to processors such as fourth-generation Intel Xeon scalable processors. The configurable and scalable architecture of Agilex 7 enables customers to quickly deploy customized technologies based on their specific needs, reducing overall design costs and development processes at large-scale hardware speeds, and accelerating execution to achieve optimal data center performance.

Compared with other FPGA competitors, Agilex 7 FPGA with R-Tile chip has leading technical strength, PCIe 5.0bandwidth is 2 times faster and CXL bandwidth per port is 4 times higher.

According to a white paper by Meta and the University of Michigan, adding FPGA with CXL memory to a fourth-generation Xeon-based server, while using efficient page placement with transparent page placement (TPP), can improve Linux performance by 18%.

In addition, UnifabriX demonstrated its CXL-enabled intelligent memory nodes in several performance benchmarks, one of which showed a 28% increase in HPCG (High performance Conjugate gradient) benchmark scores, while using more than twice the fourth-generation Xeon kernel to handle HPC workloads.

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