Shulou(Shulou.com)11/24 Report--

CTOnews.com May 5 news, according to foreign science and technology media eeNewsEurope reported that Kioxia and Western Digital (WD) will display more than 300 layers of 3D NAND in June this year.

The 2023 Symposium on VLSI Technology and Circuits will be held in Kyoto, Japan on June 11-16 this year. Xia Xia and Western Digital will publish a number of papers on 3D-NAND.

The 8-plane 1Tb 3D TLC NAND reports that the Armour will release a C2-1 paper introducing the 8-plane (eight-plane) 1Tb 3D TLC NAND with more than 210 active layers (active layers) and an interface rate of 3.2 GT / s.

The IC partnered with two companies to develop a 218-layer 1Tb 3D TLC NAND device that is very similar, with a 17Gb / mm ^ 2 density, but upgraded from 4-plane to 8-plane.

The armor says the 3D NAND program has a throughput of 205MB/s and a read latency of 40 μ s.

The new paper shows that the armor's 1Tb 3D TLC NAND device achieves an interface speed of 3.2 GT / s by reducing the data query area in the X direction to 41%, thus achieving faster data transfer between memory and the host. The armor has also implemented a monopulse double gating technology, which allows two memory cells to be sensed in a single pulse, thus reducing the total sensing time by 18%.

The NAND companies achieve more than 300 layers of 3D NAND by lengthening the vertical channel length (vertical channel length) and using metal-induced lateral crystallization (MILC) technology.

According to the T7-1 paper, MILC technology enables the creation of 14 micron "macaroni" silicon (Si) channels in vertical storage holes.

This experimental 3D NAND IC also uses cutting-edge nickel absorption methods to eliminate impurities and defects in silicon materials, thus improving the performance of cell arrays. Without sacrificing battery reliability, the reading noise is reduced by at least 40%, and the channel conductance is increased by 10 times.

"original address" is attached to CTOnews.com, which can be read by interested users.

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