Shulou(Shulou.com)11/24 Report--

Thanks to CTOnews.com netizen Xiao Zhan for the clue delivery! CTOnews.com April 27 news, on April 26, local time, TSMC held a North American Technology Forum in Santa Clara, California, to announce the latest progress and roadmap of its 3nm process. Among them, the most interesting is the N3X process, which will be put into mass production in 2025 to provide the strongest chip manufacturing capability in the field of high performance computing (HPC).

CTOnews.com learned from TSMC officials that TSMC's 3nm process family includes four versions, namely, basic N3, cost-optimized N3E, performance-enhanced N3P and high-voltage tolerant N3X. Among them, N3E and N3P are optical scaled-down versions based on N3, which can reduce complexity and cost, while improving performance and transistor density. N3X, on the other hand, is a process designed for the HPC domain and can support higher voltages and frequencies, resulting in greater computing power.

According to TSMC data, compared with 5nm process, N3E can reduce power consumption by 32% at the same frequency or improve performance by 18% at the same power consumption. Compared with N3EPermy N3P, it can improve performance by 5% at the same power consumption, or reduce power consumption by 5% to 10% at the same frequency. At the same time, N3P can also increase the transistor density by 4%, up to 1.7 times the level of the 5nm process.

The N3X is the most powerful version of TSMC's 3nm process family, which can improve its performance by 5% over N3P at the same power consumption and reach a voltage level of more than 1.2 volts. This is very extreme for a 3nm-level process and means high power consumption and heating problems. Therefore, this process is only suitable for HPC processors that require extreme performance, and chip designers need to take effective measures to control temperature and power consumption.

TSMC said mass production of N3E would begin in the second half of 2023, while N3P and N3X would go into mass production in the second half of 2024 and 2025 respectively. These processes will adopt FinFET structure, that is, metal oxide semiconductor field effect transistor (MOSFET) structure. This structure has been used by TSMC for many years and has mature and stable characteristics.

However, below the 2nm level, TSMC will adopt a new GAAFET structure, that is, the gate-enclosed field effect transistor (Gate-All-Around FET) structure. This structure can further improve the density and performance of the transistor and reduce power consumption and leakage. TSMC said that the 2nm process has made good progress in the yield of quality products and the efficiency of components, and will produce as scheduled in 2025. According to TSMC, compared with N3E process technology, the speed of 2nm can be increased by up to 15% at the same power consumption; at the same speed, the power consumption can be reduced by up to 30%, while the wafer density increases by more than 15%.

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