Shulou(Shulou.com)11/24 Report--

Thanks to the CTOnews.com netizen Mr. Air, OC_Formula for the clue delivery! CTOnews.com, April 23 (Xinhua)-- as major car companies turn to software-defined car architectures, the design of the next generation of models is facing memory problems. Due to many reasons, the traditional xSPI NOR flash memory has gradually been unable to meet the needs of users.

In order to meet the new needs of automotive regional architecture, Infineon Technology announced the launch of the industry's first LPDDR flash memory. The company combines flash memory with LPDDR interfaces to achieve higher performance and scalability than xSPI NOR flash memory.

According to reports, this new flash memory device called SEMPER X1 draws lessons from the LPDDR interface scheme of LPDRR4 DRAM, which has a history of 10 years, and applies it to flash memory.

As the figure shows, there are a large number of area controllers (green parts) in these newly designed cars. "these area controllers have a lot of real-time computing needs," said Sandeep Krishnegowda, vice president of marketing and applications at Infineon. "they don't just pass that data to the central ECU. These area controllers need to handle safety critical functions such as braking, steering and powertrain."

In order to be able to handle these real-time processing requirements, car area controllers must constantly improve their performance. "where 4K DMIPS is common, area controllers will now move to 10K, 12K, and 16K DMIPS." this more complex calculation is beyond the scope of a controller with onboard internal embedded flash memory.

In addition, with the upgrading of driving assistance and entertainment systems, the next generation of cars have a very high demand for computing power, which further promotes the upgrade of CPU core and onboard flash memory. Traditional processors are being replaced by these high-performance multi-core processors that eliminate embedded flash memory.

In fact, most of these processors are built on advanced semiconductor technology, and it is not cost-effective for developers to add on-board flash memory, so they need more flash memory to support them, but in terms of interfaces, standard xSPI NOR flash memory can not meet real-time computing / execution (XiP) requirements.

With these in mind, Infineon launched a new type of memory called LPDDR flash memory. "We have worked with some of our first-tier OEM to define this type of LPDDR flash memory to address the growing need for multicore CPU for real-time computing," said Krishnegowda. "in LPDDR flash memory, you can have multiple memory libraries, so when you have multiple kernels, any kernel can communicate with any memory library because it is essentially random access."

Krishnegowda says this approach can greatly improve execution speed. "if you compare it to a standard eight-way (x8) xSPI NOR flash device, LPDDR flash memory can improve performance by 20 times," he said. "this is what is needed now so that you can transfer what you used to calculate inside the processor to external memory for real-time computing."

CTOnews.com learned officially that SEMPER X1 flash memory can achieve a throughput of 3.2 GB / s through the LPDDR interface. According to Infineon, its multi-bank architecture supports wireless firmware updates and does not take a second. Importantly, the device complies with ISO26262 ASIL-B standards and provides advanced error correction and other security features.

Infineon said the SEMPER X1 is now out of production and is scheduled to be put into commercial use in 2024.

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