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Research institutions: existing Internet of things chips begin to adopt RISC-V architecture

2025-02-02 Update From: SLTechnology News&Howtos shulou NAV: SLTechnology News&Howtos > IT Information >

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CTOnews.com, April 17, DIGITIMES Research reported that although the pace of global development of new chips of the cellular Internet of things has slowed down, due to the spread of terminal applications in many fields, the number of devices connected to the Internet of things will continue to increase, coupled with the gradual withdrawal of 2G/ 3G, broadband communication technologies such as LTE Cat.1bis and 5G NR-Light have gradually attracted market attention, attracting Internet of things chip operators to the layout of new technologies. On the other hand, Internet of things chips using RISC-V architecture have begun to appear in the market, and whether the trend takes shape is also worthy of follow-up observation.

Due to the slowing down of the infrastructure of the Internet of things, coupled with the long life cycle of Internet of things devices and scattered applications, chip vendors will not be prompted to develop new chips unless there are new specifications or emerging applications. In addition to the mature NB-IoT and LTE-M chip markets, the development prospect of LTE Cat.1bis technology has attracted the attention of the chip industry, prompting many companies, such as Qualcomm, to launch new chips that support LTE Cat.1bis. In addition, 5G NR-Light (CTOnews.com Note: also known as RedCap) technology is the focus of the future development of the cellular Internet of things, Qualcomm has taken the lead in the industry to release the relevant chips, and predicted that there will be Internet of things devices with related chips in the first half of 2024.

The report points out that cellular Internet of things chip manufacturers, such as core technology and core wing information, have launched Internet of things chips using RISC-V architecture, as a choice to break away from the ecological circle of Arm architecture and enhance chip autonomy.

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