Shulou(Shulou.com)11/24 Report--

CTOnews.com April 13 news, according to foreign technology media SamMobile reports, Samsung plans to use fan-out wafer-level packaging (FoWLP) technology for Exynos 2400 processors.

FoWLP means smaller package size, higher integration, and can provide I / O performance. Theoretically, Exynos 2400 processors are smaller in size, stronger in performance and more energy efficient in power consumption.

CTOnews.com mini-class (the following content is from Wikipedia):

Fan-out wafer-level packaging is a kind of integrated circuit packaging technology, which is the enhancement of standard wafer-level packaging solutions. In traditional technology, the wafer is cut first, and then each die is encapsulated; then, a single die is sealed on the wafer. The package size is usually much larger than the chip size.

In contrast, in a standard WLP process, the integrated circuit is still part of the wafer when it is packaged, and then cuts the wafer into small pieces. The final package is actually the same size as the bare piece itself.

Based on previous information, the Exynos 2400 processor uses a 1-2-3-4 design:

1 Cortex-X4 core with 3.1GHz clock rate

2 Cortex-A720 cores with 2.9GHz clock rate

3 Cortex-A720 cores with 2.6GHz clock rate

4 Cortex-A520 cores with 1.8GHz clock rate

Exynos 2400 will use a RDNA2 GPU named Xclipse X940 (tentative), which contains 6 WGP (12 CU), 8 MB L3 cache, and supports hardware-level RayTracing.

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