Shulou(Shulou.com)11/24 Report--

CTOnews.com, March 5 (Xinhua)-- AMD Ryzen 9 7950X3D has become one of the most powerful game processors today, thanks to disruptive 3D chip stacking technology, but oddly enough, the company didn't mention any details about its new second-generation 3D V-Cache when it released Ryzen 7000X3D.

AMD shared some details with foreign media at a recent technical meeting. According to reports, the Chiplet chip still uses 7nm technology, but the peak bandwidth is increased to 2.5 TB / s, while the peak bandwidth of the original 3D V-Cache is 2TB / s.

In addition, we also got the new pictures and parameters of the new 6nm I / O chip of the AMD Ryzen 7000 processor.

Overall, AMD's second-generation 3D V-Cache technology is another big step forward over the first-generation technology.

First, AMD's 3D V-Cache technology places an additional L3 SRAM chip directly in the center of the computing chip (CCD) chip, isolating it from the hotter core. The chip brings 96MB 3D cache to it, which improves performance for latency-sensitive applications such as games.

AMD presented some new technologies for the implementation of the second generation 3D V-Cache at the 2023 International Conference on solid State Circuits (ISSCC) and demonstrated the Zen 4 architecture.

The previous generation of AMD 3D V-Cache stacked L3 SRAM chips on 7nm Zen 3 CCD, while the new generation of L3 SRAM chips still adhere to the 7nm process, but it needs to be stacked on a smaller 5nm Zen 4 CCD. This results in a size mismatch, so some modifications are needed, resulting in a significant increase in the transistor density.

The first generation chip 5nm Zen 4 CCD7nm Zen 3 CCD size 36mm241mm266.3mm280.7mm2 transistor number is about 4.7 billion 4.7 billion 6.57 billion 4.15 billion transistor density is about 130.6 million about 114.6 million about 9900 million about 5140 million as before, this additional L3 SRAM cache brings 4 clock clock signal delay, but the bandwidth between the L3 chip and the basic chip is increased to 2.5 TB / s, 25% higher than the previous 2 TB / s.

The L3 SRAM chip is connected to the basic module chip through two types of TSV silicon through holes. Power TSV is responsible for transmitting energy and Signal TSV is responsible for transmitting data.

In the first generation of L3 SRAM chip design, both types of TSV are located in the L3 region of the basic chip. however, with the improvement of 5nm process, the area of L3 cache on the basic chip is now reduced. As a result, even if the L3 SRAM chip of the 7nm is smaller, it now overlaps with the L2 cache (the previous generation only overlapped the L3 cache), so AMD had to change the TSV connection design in the basic chip and the L3 SRAM chip.

As the density of transistors in the 5nm L3 cache on the underlying chip increases, AMD has to expand the Power TSV from L3 to L2.

For the basic chip, AMD achieves 0.68 times effective area scaling in L3 cache, data path and control logic (compared with the old 7nm chip), so the TSV physical space in L3 cache is smaller.

The Signal TSV remains in the L3 cache area on the base chip, but AMD reduced the TSV area in the L3 cache by 50% by applying the knowledge learned from the first generation design and DTCO improvements to reduce the additional circuits in the new interface design.

CTOnews.com warned that AMD's 3D chip stacking technology is based on TSMC's SoIC technology, while TSMC's SoIC is designed without bumps, which means that the connection between the two chips does not use microbumps or solder. AMD says it uses the same basic bonding / bonding process and has made continuous process and DTCO improvements, but the minimum TSV spacing has not changed.

In addition, the L3 SRAM microchip is kept in the same power region as the CPU core, so it cannot be adjusted independently. It is precisely because the voltage cannot exceed ~ 1.15V, so the frequency of the small chip equipped with cache will not be too high.

6nm I / O chip-Ryzen 700012nm I / O chip-Ryzen 50006nm I / O chip EPYC size 117.8mm2125mm2386.88mm2 transistor number 3.37 billion 2.09 billion 11 billion transistor density ~ 28.6 million ~ 16.7 million ~ 29.8 million

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