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2025-01-19 Update From: SLTechnology News&Howtos shulou NAV: SLTechnology News&Howtos > IT Information >
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This article comes from the official account of Wechat: knowledge Automation (ID:zhishipai), author: Bao Yungang
Original title: "Bao Yungang | Chip Breakthrough"
The neglected microarchitecture capability of reduced instruction set RISC is a legend in the history of calculator chip development. Its most proud work, in 1983, the British company Acorn, launched a new processor architecture research and development project Acorn RISC Machine (ARM) based on the concept of the University of California, Berkeley RISC project, which is the beginning of the ARM architecture that now dominates mobile chips. Berkeley's RISC project developed four generations in the 1980s and launched the fifth generation of design, RISC-V, in 2010.
RISC-V is a set of instructions, not an implementation of a processor. Instruction set is a standard specification, which is equivalent to everyone's agreement. If you follow the same standard specification, then the software and hardware produced by different manufacturers can work together, just like the size specification of screw nut.
With the instruction set standard specification, the next most important step is chip design. Complete the design of the micro-architecture according to the instruction set, form the document, and then form the source code through engineering development. With the source code, the EDA software can be used to form the chip layout, and finally handed over to these contract factories such as TSMC or SMIC to stream the chip to achieve chip manufacturing.
When many people focus on manufactured equipment or designed software, it is easy to quietly ignore the invisible "design and implementation of micro-architecture". In fact, this is a very important capability and the core competitiveness of chip design.
When you have the ability to design and implement microarchitecture, it will no longer be limited to the instruction set. It will also be very easy to change an instruction set. What is the reason for the continuous improvement in the performance of Intel processors over the past few decades? The increase in the instruction set is a visible accumulation, but more importantly, the microarchitecture and technology of Intel processors continue to evolve. From Intel's P6 architecture in 1995 to 2000 to 2006, the architecture evolves about every five years. In the process of continuous iteration, the optimization at the micro-architecture level is realized. And this is the core of Intel's design capabilities. Even from this point of view, the instruction set is not that important to some extent, because it is just a standard specification. The design and implementation ability of micro-architecture really determines the performance, power consumption and area of a chip. Apple has changed a number of instruction sets over the past few decades, from Motorola to Intel to PowerPC to today's ARM. Because of Apple's own strong vertical collaborative design ability, it is not too difficult to change the instruction set. Because of its strong chip design ability, the domestic Godson company hardly needs to change its micro-architecture design from MIPS instruction set to its own instruction set Godson (LoongArch) instruction set. There are domestic enterprises in research and development can support both Arm and RISC-V design, but also because the underlying micro-architecture design does not need a big change to support different instruction sets.
Are instruction sets and ecological instruction sets no longer important? In terms of software ecology, it is very important. It will determine the efficiency of software ecological development. In the early days of IBM computers, the instruction set of each computer was independent, resulting in a large investment in computer software. The System / 360computer launched by IBM in 1964 changed this pattern and formed a unified set of instructions, so that computer software and hardware can be separated. This standardized instruction set extends, gradually making it possible for an independent software industry. Although the unified instruction set is not as important as the architectural capability to the role of a single company, it has a decisive impact on the software ecology.
However, in the past few decades, instruction sets have been privately owned by companies, such as X86, ARM, MIPS, SPARC, and so on. In 2010, Professor David Patterson of the University of California, Berkeley, put forward a loud slogan "instruction sets should be free", which was immediately accepted all over the world. The RISC-V launched by Berkeley is booming. Since the instruction set no longer belongs to a company, the whole world can build it together. A new open source, open and shared processor ecology has emerged. The core of the co-construction model is to separate the standard specification from the product implementation. This is very similar to the construction mechanism of 5G communication standard in the field of communication. The 5G standard is formulated by the non-profit organization 3GPP, and each enterprise can make its own products according to the 5G standard and compete in an open mode.
Similarly, RISC-V brings such a new opportunity, and the standard of the instruction set is set by the RISC-V International Foundation. Based on this standard, different enterprises in different countries can develop different RISC-V products, such as the RISC-V products of Sifive, the rookie of Silicon Valley in the United States, the Xuan tie RISC-V processor of Ari Pingtou in China, and the Xiangshan processor being developed by the Chinese Academy of Sciences. This brings a new mode, "5G mode development chip", for the processor manufacturers who enter the track. In the past 20 years, the main modes of domestic processor development are "high-speed rail mode" and "Beidou mode". The high-speed rail model represents a way to integrate into the existing ecology, through introduction-digestion-absorption-re-innovation to achieve product upgrading, on behalf of enterprises such as Haiguang, Hayes and Feiteng. The Beidou model is an independent construction of technical system and ecology, represented by Longxin and Shenwei. The "5G mode" means that Chinese processors can adopt the third mode, formulate open standards, develop their own core technologies, compete and cooperate under an open framework, and face the international market and ecological construction.
Although the re-understanding of RISC-V is of great significance, there are still many misunderstandings in the industry. In December 2022, Professor David Patterson wrote an article devoted to correcting some fallacies about RISC-V.
The first misunderstanding is that RISC-V is an open source processor, just like Linux is an open source operating system. In fact, RISC-V is not an open source processor, it is just a standard specification and is essentially a descriptive manual, similar to Ethernet standards, USB standards, and so on. The Linux operating system is a kind of source code. So these two are not comparable. RISC-V is a standard, and the International Foundation is similar to a working group to develop standards and specifications.
The second misconception is that a mature closed instruction set is more secure than choosing an open instruction set. Security has nothing to do with closed and open source. The closed instruction set belongs to the company and will be closely bound to the fate of the company. If the company is depressed, the company's instruction set will disappear and the security of the supply chain cannot be guaranteed. There are many instructions that have disappeared in history, including instruction sets such as DEC VAX and DEC Alpha, which were once popular. In addition, the closed instruction set may not be stable. MIPS was sold to six companies that year, and ARM has three owners, and changing one owner means that the business model may change.
The third misconception is that a closed instruction set is in a uniform, fragmented state. In fact, closed instruction sets often encounter unforeseen incompatibility problems in their life cycle. Even under one of the ARM systems, there have been incompatibilities. ARMv1 to ARMv7 uses 32-bit address space, but ARMv8-a, which can provide both 32-bit and 64-bit address versions in the next generation, is not compatible. Moreover, even if the same generation of products, ARMv8-an and ARMv8-m are not compatible. Fragmentation is actually a kind of normality to some extent.
The fourth misconception is that the modularization of RISC-V leads to a more fragmented software ecology than a closed instruction set. At this point, the RISC-V Technical working Group is already providing some new mechanisms, such as Profile mechanisms, to regulate the software ecology so that the software is not as fragmented as expected.
As a final fallacy, many people assert that RISC-V cannot become a mainstream instruction set. It is too early to draw this conclusion. Technically, RISC-V can support from embedded, to ordinary computers, to supercomputers, and there are no systematic defects. From a commercial point of view, more open standards tend to be more dynamic. This is comparable to the success of the Linux operating system.
RISC-V 's five major trends RISC-V has begun to develop into high-performance areas. In the past, many people thought that it could only be used in the embedded field, but in recent years, there have been a number of RISC-V high-performance processor implementations, which represent Silicon Valley's Sifive and Ventana, which have certain advantages in technology. There are also Xiangshan processors and Shanghai Sai Fang in China. SiFive recently launched a RISC-V processor up to 3.4GHz, which can match the performance of ARM A78 and is a very high performance processor. Compared with the domestic point of view, in the progress of research and development, this design is ahead of the domestic Xiangshan for about a year. But Xiangshan also has its advantages, because Xiangshan through open source open mode of joint research and development of multiple enterprises, can be faster iteration, while reducing costs through sharing.
It is worth noting that many countries are actively promoting or supporting RISC-V at the national level. For example, in June 2022, the Russian Ministry of Digital Development announced that it would vigorously support the development of RISC-V processors. India has also launched the Digital India RISC-V processor (DIR-V) Development Plan. At the same time, India's Ministry of Electronic Information (equivalent to the domestic Ministry of Industry and Information Technology) joined the RISC-V International Foundation in the name of the Ministry and became a senior member. In addition, on September 8, 2022, the EU issued a report on "recommendations and Roadmap for establishing European Open Source hardware, Software and RISC-V Technology sovereignty", supporting RISC-V and open source hardware, in particular, giving nine priority key directions and implementation paths, including the establishment of non-profit institutions to support research and development, the implementation of education policies and measures, and so on. Thus it can be seen that the whole world is actively involved in the ecological construction of RISC-V.
The key software ecology of RISC-V is also developing very rapidly. On the one hand, the RISC-V International Foundation is actively promoting the adaptation of basic software; on the other hand, many open source software communities are also actively adapting. This makes the software forces all over the world also support the development of RISC-V ecology. Take Debian, the Linux distribution, as an example. The open source community began to support RISC-V in 2019. Thanks to the efforts of the open source community around the world, it took only 3 years to complete the migration of 95% of more than 20,000 software packages, making RISC-V a Tier-1 architecture supported by Debian. China is in the first echelon in the ecological construction of RISC-V. Especially since 2018, many enterprises have been launching a variety of RISC-V-based chip products. At the same time, the local government also issued a series of policies. The Beijing government, in particular, has a lot of investment in RISC-V.
As the RISC-V software ecology is also accelerating, RISC-V is being supported by more and more enterprises. In addition to startups, giants like Intel are also actively involved in the ecological construction of RISC-V. American enterprises have invested a lot in the field of high-performance processors and are in a leading position on the whole. But at home, startups are very active and the number is much larger than in the United States. At present, though, it is still mainly concentrated at the MCU level. But this has injected a little fresh air into the monopolistic markets of Europe, the United States and Japan.
On the whole, RISC-V applications are growing rapidly around the world. According to data from the RISC-V International Foundation in the first half of 2022, RISC-V shipments have exceeded 10 billion and are expected to exceed 80 billion by 2025. Generally speaking, RISC-V still lacks some milestone, benchmarking RISC-V applications. But the good news is that the European Union plans to spend 270 million euros on supercomputers, which will be a milestone.
China's Flower RISC-V International Foundation, as the standard-setting institution, is currently very active. In the world, more than 70 countries and more than 3000 members have joined the RISC-V International Foundation, and it has been growing at a rate of more than 100% every year in recent years. From the perspective of national distribution, China, the United States and Europe are neck and neck. China's domestic enterprises have a very high degree of participation. Among the senior members of the RISC-V International Foundation, 14 domestic enterprises are senior members; of the 25 global directors, 9 are from China; and there are some technological development partners, and Chinese institutions and enterprises are also actively participating. This is a very dynamic organization in China.
With the support of Beijing and the Chinese Academy of Sciences, 18 enterprises have jointly launched the Beijing Open Source Chip Research Institute (Kaixin Institute), which is a senior member of the RISC-V Foundation. The Open Source Chip Research Institute hopes to build an open source chip ecology like open source software. In such an open source chip ecology, there are many open source hardware components that can be fully reused, thus greatly reducing the cost of building a chip and further allowing more small and medium-sized enterprises to release their innovation vitality.
At present, Kaixinyuan has launched the research and development of Xiangshan open source high-performance processor core. Its goal is to be like Linux. As before, Linux and RISC-V are not at the same level, but Xiangshan and Linux are at the same level. RISC-V is a standard specification, while Xiangshan is a concrete implementation. RISC-V itself is not like Linux, but Xiangshan is like Linux. Xiangshan of the Open Source Chip Research Institute is positioned as a mainline similar to Linux open source processors, which can not only be widely used in industry, but also support academia to do innovation.
The characteristic of Xiangshan is that its source code is open source, and the entire platform and tools for developing code are also open. Using an iceberg as an analogy, the chip itself can be regarded as the part above the iceberg water, and the part below the iceberg water is how to design a series of infrastructure, testing and verification tools for the chip. Xiangshan, is to make all these contents open source, so that we can unite more enterprises to research and develop together. At present, the architecture design of Xiangshan has developed to the third generation. The first generation, called Yanqi Lake, was filmed at the beginning of 2022 and achieved the expected performance. The second generation, called "South Lake", has now achieved the delivery of the first customer. South Lake's performance is on a par with the ARM A76 level and continues to iterate over new versions. Xiangshan, a chip design built through open source mode, has been strongly supported by open source communities all over the world. Since its release in 2021, Xiangshan has been very active on GitHub and is one of the most active open source chip projects in the world.
Xiangshan is no longer a scientific research project of the Chinese Academy of Sciences, but through organizations such as Kaixin Academy, which connects academic and industrial circles, to achieve product-oriented, industrial-level delivery capacity.
From the performance comparison chart, Xiangshan currently has the highest performance among the open source chips in the world. On this basis, Kaixinyuan further determined the development goal of "two cores". The first is the classical core, which can be applied to the processor core of mid-and high-end industrial and pan-industrial technology platform, ARM A76. The second core is a high-performance core, which is mainly used in high-performance scenarios, such as data centers, computing infrastructure, etc., to align ARM N2. At present, the classic core "Nanhu" (performance standard ARM A76), Kaixinyuan also achieved smooth delivery in November 2022, that is, 100% of the RTL code was delivered to the first user on schedule. In the process of cooperation, it is also highly appraised by users. Next, Kaixinyuan will deliver Nanhu to a second user in February this year.
Longer-term plans are also being followed. In August 2022, the joint research and development of the third generation of Xiangshan "Kunming Lake Architecture" formed a R & D team of about 100 people, which opened the curtain for the new future.
Lighter and wider: the fourth-generation chip business model is a question that many people are very concerned about: is there a future for open source chips?
This question can be inspired by history. IBM launched the personal computer in 1981 and made all the documents public. Today, people can still find the nearly 400-page document that IBM made public that year. This document contains all the source code, circuit diagrams, and the configuration of various registers. This was a very shocking move in the highly competitive and incompatible personal computer market at that time.
It has brought two far-reaching effects: the first impact is the birth of a number of new enterprises, such as Dell, Compaq, as well as domestic Lenovo and the Great Wall. Dell and Lenovo were both founded in 1984 and are still the dominant players in the world (the other is the established Hewlett-Packard). As a result of lowering the threshold of personal computer design, many enterprises can enter the personal computer field to find a new space for enterprise development. The second impact is a substantial reduction in the price and cost of the PC. The original PC costs nearly US $10,000. Because of the open source of IBM, the price of PC has been reduced to US $1500, making PC truly accessible to every household and creating an emerging PC market.
Open source chips have the same potential to activate a larger industry, that is, the emerging IoT industry of "man-machine-object" integration. The industry will be even bigger because the Internet of everything and man-machine interconnection are everywhere, whether it's smart homes or car networking. So in the past few decades, in the face of different industries, how do different chip companies support it? An interesting phenomenon is that the more open the enterprise model is, the less resources are needed, but the industry is getting bigger and bigger.
Intel's model is "IDM mode + selling chips", enterprises can only use Intel chips to do the whole machine. This model can be seen as a heavy asset model, so Intel needs more than $50 billion in turnover and tens of billions of dollars in profits to support the PC industry. The Nvidia model, which started with the image GPU, is lighter than the Intel model, using the "unmanufactured chip design Fabless mode + chip sales" model, which only needs a turnover of more than US $15 billion and a profit of US $3 billion to dominate the world and support the development of the artificial intelligence industry. The third-generation model is British ARM, with lighter assets. It uses the "Fabless+IP license" approach, only do IP and let other companies do chips. So ARM, which only needs US $2 billion in turnover and US $300m in profit, can dominate the smartphone industry all over the world.
Now the Internet of things is a depression if the open source chip, IP, development tools can be realized open source open, it will pry the market will be bigger. Through non-profit organizations such as Kaixinyuan, adopting the model of "joint Fabless + shared IP license", only 200 million US dollars in R & D funding is enough to shake up a rich Internet of things industry. More startups will have the ability to quickly customize chips according to the needs of the scene. Open source chips will have a very broad prospect.
Note: open source is a road worth trying. RISC-V opens a unique way for collective intelligence to develop chips. Considering the security of the global supply chain, open source chips are timely. Its contribution to innovation is not only technology, but also subversive changes in the organization and business model. Chips are about the future, and open source has opened up a whole new world.
A brief introduction to the author
Author
Bao Yungang: Institute of Computing, Chinese Academy of Sciences / Beijing Open Source Chip Research Institute
Compilation and examination
Lin Xueping: general Manager of Beijing Lianxun Power Consulting Co., Ltd.
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