Shulou(Shulou.com)11/24 Report--

CTOnews.com, December 11 (Xinhua) it is well known that traditional integrated circuit technology uses planar expanded electronic and hole transistors to form complementary structures to achieve high-performance computing power, but the increase in transistor density is mainly achieved by reducing the size of cell transistors. For example, the most common case is the high-precision size miniaturization of the semiconductor industry, which has been iterated at a rate of 0.7 from 14 > 10nm > 7nm > 5nm (which does not represent the actual gate distance).

According to an official announcement from the School of Microelectronics of Fudan University, Professor Zhou Peng, researcher Bao Wenzhong and Wanjing team of the School of Information Science and Engineering bypassed the EUV process and developed a heterogeneous CFET technology with excellent performance. CTOnews.com learned that the results have been published in the journal Nature Electronics.

To put it simply, researchers have creatively designed a wafer-level silicon-based two-dimensional complementary laminated transistor, which can double the device integration density under the same process node, thus achieving excellent electrical performance.

Officials say that the equipment of extreme ultraviolet lithography is complex, and the technology value of three-dimensional stack complementary transistor (CFET) which can greatly increase the integration density under the existing technology node is prominent, but the process complexity of all-silicon-based CFET is high and the performance is seriously degraded in the complex process environment.

According to reports, this kind of silicon-based two-dimensional complementary laminated transistor integrates a new two-dimensional material on a silicon-based chip using a mature back-end process, and uses the highly matched physical characteristics of the two to realize a 4-inch large-scale three-dimensional heterogeneous integrated complementary field effect transistor.

This technology can realize the wafer-level heterogeneous CFET technology. Compared with silicon, the single atomic layer thickness of two-dimensional atomic crystal makes it have superior short channel control ability in small size devices. This technology will further improve the integration density of the chip and meet the development needs of applications such as high-power processors, high-density memory and artificial intelligence.

The concept, wafer-level fabrication and device structure diagram source of ▲ silicon-based two-dimensional stack transistors: Fudan University official website

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