Shulou(Shulou.com)11/24 Report--

Thanks to CTOnews.com netizens OC_Formula and Wu Yanzu in South China for their clue delivery! CTOnews.com, December 5, 2008. At the recent IEDM 2022 (2022 IEEE International Electronic Devices Conference), Intel released a number of breakthrough research results to continue to promote Moore's Law over the next decade and finally integrate a trillion transistors in a single package.

According to reports, Intel researchers have demonstrated the following research results: new developments in 3D packaging technology that can increase density by another 10 times; new materials for miniaturization of 2D transistors beyond RibbonFET, including ultra-thin materials only three atoms thick; new possibilities for energy efficiency and storage to achieve higher performance computing; new developments in quantum computing.

Intel implements quasi-monolithic chips through the next generation of 3D packaging technology:

Compared with the results announced on IEDM 2021, the latest hybrid bonding research presented by Intel on IEDM 2022 increases power density and performance by a factor of 10.

By miniaturizing the interconnection spacing to 3 microns through hybrid bonding technology, Intel has achieved interconnection density and bandwidth similar to that of monolithic system-on-chip (system-on-chip) connections.

Intel is exploring integrating more transistors on a single chip through ultra-thin "2D" materials:

Intel demonstrated a full-surround gate stacked nano-wafer structure using a 2D channel material only three atoms thick and a near-ideal low-leakage current double-gate transistor switch at room temperature. These are two key breakthroughs needed to stack GAA transistors and exceed the inherent limitations of silicon materials.

The researchers also demonstrated the first comprehensive analysis of the topology of 2D electrical contact materials, which is expected to further pave the way for the creation of high-performance, scalable transistor channels.

To achieve higher-performance computing, Intel brings new possibilities for energy efficiency and storage:

By developing memories that can be placed vertically on top of transistors, Intel has redefined miniature technology to make more efficient use of chip area. Intel is the first in the industry to demonstrate stackable ferroelectric capacitors (stacked ferroelectric capacitors) with performance comparable to traditional ferroelectric groove capacitors (ferroelectric trench capacitors), which can be used to build ferroelectric memories (FeRAM) on logic chips.

The industry's first device-level model, which locates the mixed phases and defects of ferroelectric oxidation devices (ferroelectric hafnia devices), marks Intel's significant progress in supporting industry tools to develop new memories and ferroelectric transistors.

Intel is blazing a path to build a 300mm silicon-based gallium nitride wafer (GaN-on-silicon wafers), achieving 20 times the gain of the industry standard and breaking the industry record for high-performance power supply indicators.

Intel is making breakthroughs in ultra-energy-efficient technologies, especially transistors that retain data in the event of a power outage. Intel researchers have addressed two of the three obstacles that prevent the technology from being fully implemented and put into use at room temperature.

Intel makes more powerful qubits for quantum computing:

Intel researchers have deepened their understanding of various interface defects (interface defects), which can become environmental interference (environmental disturbances) that affect quantum data, thus finding a better way to store quantum information.

CTOnews.com learned that Dr. Ann Kelleher, executive vice president and general manager of technology development at Intel, will host a plenary session at IEDM 2022 to mark the 75th anniversary of the birth of the transistor. At that time, Kelleher will outline the path of continuous innovation in the semiconductor industry, which is to unite the entire ecosystem around a system-level strategy to meet the world's growing computing needs and achieve innovation in a more efficient way, thus moving forward at the pace of Moore's Law. The meeting will begin at 09:45 PST on Monday, December 5 (01:45 on Tuesday, December 6, Beijing time) with the theme "Celebration of the 75th Anniversary of the birth of Transistors! the Evolution of Moore's Law Innovation".

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