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This article comes from Weixin Official Accounts: Knowledge Automation (ID: zhishipai), original title: Lin Xueping| Beyond Moore's EDA Software Four King Kong, by Lin Xueping

Before the four diamond chips of EDA software enter large-scale production, they need to carry out "trial production," that is, flow chip, and produce several or dozens of pieces of completed design circuit first. Tape-out is an extremely expensive process.

In the era of 14-nanometer processes, a tape-out cost about $3 million. At 7 nm, the cost of tape-out is as high as $30 million. In order to prevent reckless waste, simulation tests need to be performed on electronic design automation (EDA) software. Even if the cost of all the design tools were added up, it would not cover the cost of a single tapeout. Therefore, it is necessary to pass simulation on the software to ensure that nothing is wrong before it can really start streaming.

So what is "foolproof"?

This is a process called Sign-off. On a long list, power consumption, noise, heat dissipation, static electricity, etc. need to be signed off one by one. Only validated EDA software simulations will be accepted by wafer fabs.

Whenever TSMC holds an industry conference, the entire semiconductor industry almost always listens. It refers to many proven tools and programs. For the industry, no matter which scheme, it will move closer to it. After verification by TSMC, it has become the gold standard in the industry and the mainstream choice.

For electronic design automation software, TSMC mainly recognizes four EDA manufacturers collectively known as MACS, namely Synopsys, Cadence, Mentor, and Ansys, a leading enterprise in the field of simulation CAE. Ansys 'sharp edge in EDA software seems to be obscured by the light of its overall brand, but it does not affect its EDA software to become one of the gold standards in the industry. EDA software four King Kong, also in the joint efforts to dominate the direction of chip development.

The global EDA market concentration is quite high, if only from the EDA software (excluding IP), then the market share of the four kings can reach 80%, American suppliers occupy a dominant position. The remaining market share is divided by many other EDA software, including Altium of Australia, Silvaco and Aldec of the United States, etc., while domestic companies such as Gailun Electronics and Huada Jiutian have been listed successively this year. But in the U.S., there hasn't been a new EDA listing in two decades. Globally, this market is showing signs of maturity. However, EDA software is a pioneer in the semiconductor industry, and it is brewing a whole new meaning in order to adapt to the latest trends in chip manufacturing.

Atoms live in new palaces No doubt Chiplets have been one of the focuses of the last two years. However, it should be pointed out that three-dimensional packaging technology has a long history, and advanced semiconductor manufacturing has been carried out in two ways for many years.

The first road is to advance in the direction indicated by Moore's Law according to the law of node evolution. Moore's Law is a comfortable shortcut, and the one thing that makes semiconductor planners happy is that technology roadmaps are definitive. The warm lighthouse has been shining steadily for more than six decades, but its light is fading and there are fears it will lose its final glow. Advanced processes are approaching the size of a nanometer. It is like an infinitely smaller sword entering the palace inhabited by countless atoms, and the atoms that wander at will show surprise, anger, and unpredictable new characteristics in the face of uninvited guests. Atomic size is the smallest bulwark that keeps the microworld intact, and it's also the ultimate battleground in the physical world of chips. Atom-based partition would be Moore's law's final glory.

In the post-Moorish era, it is necessary to find a new source of light for this soon-to-be dusty lamp.

The second path, in fact, the industry has long seen, but this road is sparsely populated. Japan has been considering the route of 3D packaging since the 1980s. Simply put, it is like building a three-dimensional tall building in the vertical direction of a two-dimensional plane. Because of the accessibility and efficiency of the first route, people are not enthusiastic about this path. However, with the arrival of the post-Moore Law era, chip technology encountered a cold pair of atoms in the main road and the south wall suddenly rose, so 3D packaging, this non-mainstream way, has now become a brand new weapon. Chiplet chiplets begin to appear. By combining many small chips with each other, a system-level large chip is constructed.

This is a systematic thinking, which realizes the stereo integration of various isomorphic and heterogeneous circuits. Even better, it's a "software-on-a-chip" approach. Each chiplet can be viewed as a subfunction of some software. These small chips will be moved around and assembled in the form of "software calls." This kind of building block is essentially a kind of knowledge reuse. Each small chip has unique skills and has experienced Moore's Law.

So the way the chip is packaged does not mean the collapse of traditional fin-shaped field effect transistors. On the contrary, with a small chip, the finned tube's limits can continue to be excited. The two are actually complementary routes. Each subfunction still needs to be optimal; each chiplet still needs to be optimal. "Transcending Moore" is not to break Moore's Law and find another way, but to surpass it only by standing on the towering shoulders of Moore's Law.

Advanced encapsulation is not a superposition of simple encapsulation. This is unlikely to be a battle that can only be waged by traditional downstream package manufacturers. This was destined to be a gunshot from the design source of the wafer processing plant. Whether it is an advanced package or a small chip, it can only start from the chip design. The baseline for this route, with high probability, can only be advanced by chip manufacturers, not traditional packaging companies.

Atoms can be happy. The flat houses they are accustomed to will rise into tall buildings. Tiny chips start to have lots of neighbors. However, they are also entering a macro world of large size. Heat, electromagnetism, force, and other unrelated physical effects pass through the hall like an increasingly fierce westerly wind, and the once negligible whistling sounds become sharp. Multiple physical field effects, which are more pronounced at macroscopic size, are beginning to pose a serious threat to the new halls of atoms. Heat dissipation, warpage, etc. have become huge challenges in chip manufacturing.

Chip designers, happy to build new palaces for atoms, must figure out how to cope with the effects of multiple physical fields. Omnidirectional simulation is naturally an essential tool. This point, in the eyes of aviation, machinery, automotive and other engineers, has long been a common challenge. Ansys is the leader in multiphysics simulation, providing skilled engineers with a handy tool.

From the earliest mechanics, Ansys gradually expanded its territory to fluid, thermal, electromagnetic, photoelectric and other physical fields. Even the simulation market in the field of semiconductor EDA software has been painstakingly managed for many years. The current small chip, on the other hand, makes its multi-physics simulation function particularly dazzling.

The new era of EDA software has arrived.

Late 3G, a step ahead of the judgment As early as April 2008, Ansys, which has established a king position in the field of mechanical manufacturing simulation, acquired EDA manufacturer Ansoft for $540 million, which established its own unique advantages in the field of high-frequency simulation of circuit boards. HFSS, the industry's gold standard for electromagnetic field simulation software, once occupied 80% of the market share of electromagnetic field and RF circuits.

Through this acquisition, Ansys entered the chip industry directly. However, this breakthrough into semiconductors was once considered a failed acquisition. The acquisition took place at a stock market high, and two months later the financial crisis hit unexpectedly and the stock market plummeted. It looks like a losing proposition.

For the mobile phone market in 2008, the long 2G communication is coming to its end. Since 1995, China has entered the 2G era. In addition to phone calls, texting is starting to take off. This was Nokia's long and distant reign of supremacy. The transition from 2G to 3G has taken much longer than people think. By 2009, China officially issued 3G licenses, which took 14 years. In contrast, it took just over four years to issue 3G to 4G licenses.

And Ansys squeezed into the halls of the electronics industry at the moment when the communications revolving door switched. Beginning in 2009, 3G communications finally picked up the upward curve, bringing prosperity to the entire electronics industry. In 2010, Apple's iPhone 4 began to establish its market position, and the chips began to become more and more complex. With the huge pull of the communication industry, there are more and more requirements for high-speed and high-frequency simulation of chips. Ansys 'acquisition of ANSOFT has become a forerunner.

Apache Design Solutions, a 2011 chip power design software company that was in a quiet period before going public, was unexpectedly acquired by Ansys for $310 million. At this time, Ansys 'revenue was only 700 million US dollars, but its market value reached 6 billion US dollars, and the capital market gave full confidence to the future of the enterprise.

The acquisition stems from Ansys 'judgment on the future direction of chips.

Chip composition, generally speaking, there are three methods, respectively, chip level (Chip), packaging level (Packaging) and by the PCB board will be connected together to form a system (System). Each of these three levels has its own affliction to deal with.

A circuit on a chip is only a dozen to a few hundred atoms wide. Hundreds of millions of gate circuits will be distributed in a small space, and the power consumption and static electricity of the chip will become obstacles that engineers need to face.

Then there is packaging, to protect the tiny dust-like chip with packaging to avoid dust and moisture damage to the chip. There are a lot of electromagnetic and thermal effects involved.

Finally, it is necessary to connect multiple chips through the circuit board, and provide external interfaces, combined with the operating system and software, to form a system.

Ansys innovatively combines these three parts to consider its simulation problem, and optimizes the comprehensive performance from the perspective of integrated CPS (Chip-Package-System). This is the kind of simulation that is needed to fast-forward time to the future and reverse chip development at the other end of Moore's Law. Better chips can only be provided if the chip-package-system troika is perfectly combined.

Ansys already has system-level and package-level simulation software, and Apache is a chip-level product. Three links, is the best choice. From Apache's perspective, even if a successful IPO brings temporary technological leadership, long-term independence is still a question mark.

In this case, Ansys was able to successfully include Apache in its pocket. Apache is a big fish in a narrow niche in the EDA software market. Its RedHawk software plays an important role in semiconductor power design optimization and chip power supply. It can help mobile phone or laptop engineers easily achieve power saving needs. RedHawk single-handedly made low-power design the king of a niche rather than a function button on an EDA tool. It once occupied 90% of the global market in the global low power consumption field, thus becoming the gold standard of TSMC.

EDA software one vertical and one horizontal EDA software is like a chip development with a knife guard, but each has a division of labor.

Ansys is different from other EDA manufacturers in chip design field, mainly focusing on chip signature and simulation. Synopsys and Cadence software focus more on the process of chip design, completing the process from architecture, function to schematic and layout design and verification.

For chip design, it is far from enough to complete basic design verification, but also need to consider signal integrity and power integrity issues, as well as chip heat and thermal integrity issues, more thermal deformation, thermal stress and material characteristics of the structural integrity issues. Chip damage is often not caused by overpressure or misoperation. The real killer is heat, which is responsible for about three-quarters of chip failures. This is exactly what Ansys solves, building a line of defense for chip design.

If you take an airplane as an analogy, the other three EDA software mainly do the longitudinal body of the airplane, and the airplane needs lateral wings to take off smoothly. This wing is where Ansys focuses. There are both vertical design flow and horizontal sign-off flow, one horizontal plus one vertical, EDA four diamond software MACS together to finally complete the chip design.

Simply put, it is easier to notice a "vertical" design than to ignore a "horizontal" simulation. The earliest ancestor of EDA software came from Berkeley. But SPICE, the first EDA software, actually started with simulation. Hundreds of transistors were relatively easy to draw. Simulation, however, requires more complex partial differential equations to be solved. It can be said that EDA software from the beginning of the birth of the day, with a strong simulation smell.

EDA software has been separated from simulation software in the mechanical industry for a while, and the two seem to go their separate ways. And now, two paths that were once separate are beginning to converge.

If you open the previous phone case, you will find that the phone is basically hollow, some of the other side is empty territory. Today's mobile phones are basically solid, because they have too many functions and have to be packed with integrated circuits, and there is almost no extra space. This makes all kinds of interference, heat conduction, etc., affect each other, and the problem of multiple physical field effects is amplified in a straight line.

Cell phones are too crowded. If the chip looks at it from a human perspective and it needs to drag its family with it, its happiness must have declined sharply in the last decade or so. Because the "per capita space" area of chips is getting smaller and smaller. Because the physical size of the mobile phone needs to be combined with the size of the human hand, the size that can be operated by one hand is the ceiling of the mobile phone space. Whether it is thermal analysis, electromagnetic, high-speed signals, or simulation of packaging structures, it must be combined to cope with this increasingly crowded space. As a full-flow simulation solution from chip to package to large systems, Ansys helps designers lock in confidence ahead of time, filling each space with chips without fear of failure.

Note: Small size universe Whether exaggerated or not, the meta-universe is taking on a breathtaking picture. There, everything is nested and mirrored, the depth of field around people is replaced, and the grand view of life is rewritten. The core power of the metaverse came from the chip, which was the source of the atomic force. Nvidia is putting all its effort into the Meta Universe, and its full collaboration with Ansys is a reminder of the decisive role simulation plays in a world where virtual and real merge. And at the top of the chip manufacturing spectrum, EDA software is significantly increasing its simulation capabilities. Only by doing so can Moore's Law be overcome.

Lin Xueping: General Manager of Beijing Lianxun Power Consulting Company, Founder of Nanshan Industrial College

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