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TSMC announces the establishment of a 3D Fabric alliance to accelerate the development of 2.5D and 3D chip products

2025-03-28 Update From: SLTechnology News&Howtos shulou NAV: SLTechnology News&Howtos > IT Information >

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Thank CTOnews.com netizens for the delivery of vegetable clues! CTOnews.com October 28 news, yesterday TSMC announced the establishment of an open innovation platform 3D Fabric alliance to promote the development of 3D semiconductors. So far, 19 partners have agreed to join, including Micron, Samsung memory and SK Hynix.

This alliance is the sixth open innovation platform (OIP) alliance of TSMC. TSMC said that the 3D Fabric Alliance will help customers achieve rapid implementation of chip and system-level innovation, and use TSMC's 3D Fabric technology, which consists of a complete series of 3D silicon stacking and advanced packaging technologies, to achieve next-generation high-performance computing and mobile applications.

CTOnews.com learned that at present, most high-end processors are monolithic, but with the increasing cost of cutting-edge manufacturing technology, the design approach is shifting to multi-chip modules. In the next few years, multi-chip system packaging (SiPs) is expected to become more widespread, and advanced 2.5D and 3D chip packaging technologies will become more important.

Although multi-chip SiP is expected to simplify the development and verification of highly complex designs, they require entirely new development methods because 3D packaging brings many new challenges. This includes new design processes, new power transmission methods, new packaging technologies and new testing technologies required for 3D integration. In order to take full advantage of TSMC's 2.5D and 3D packaging technologies (InFO, CoWoS and SoIC), the chip development industry needs the entire ecosystem to work together on chip packaging, which is the purpose of the 3DFabric alliance.

Dr. Lu Lizhong, a researcher at TSMC and vice president of design and technology platform, said: "3D silicon stacking and advanced packaging technology have opened the door to a new era of chip-level and system-level innovation, while requiring extensive ecosystem cooperation to help designers find the best path among countless choices and methods."

TSMC's 3DFabric Alliance brings together developers of Electronic Design Automation (EDA) tools, intellectual property suppliers, contract chip designers, memory manufacturers, advanced substrate manufacturers, semiconductor assembly and testing companies, and equipment manufacturing groups for testing and verification. The alliance currently has 19 members, but more new members are expected to join over time.

As the leader of the alliance, TSMC will formulate some basic rules and standards. At the same time, members of the 3DFabric Alliance will jointly define and jointly develop some specifications of TSMC's 3DFabric technology, and will take the lead in obtaining TSMC's 3DFabric roadmap and specifications to align their plans with those of the fabs and other members of the alliance, and to be able to design and optimize solutions compatible with the new packaging methods.

Ultimately, TSMC wants to ensure that members of the 3D Fabric Alliance will provide their customers with compatible and interoperable solutions for the rapid development and verification of multi-chip SiP using 2.5D and 3D packages.

For example, in order to unify the design of the ecosystem with qualified EDA tools and processes, TSMC developed its 3Dblox standard. 3Dblox covers all aspects of building multi-chip devices using 2.5D and 3D packaging methods, such as chip and interface definitions, including physical implementation, power consumption, heat dissipation, electromigration IR drop (EMIR), and timing / physical verification.

Eventually, TSMC envisages that the alliance will greatly simplify and streamline the process of developing more advanced chips, especially for small and medium-sized companies that rely more on external IP / designs. For example,

Although large companies such as AMD and Nvidia tend to develop their own IP, interconnection and packaging technologies, multi-chip SiP is expected to enable small companies to develop complex chip processors. For them, standard third-party IP, rapid time-to-market, and proper integration are key to success, so 3D Fabric alliances are critical to them.

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