Shulou(Shulou.com)11/24 Report--

Thanks to CTOnews.com netizen OC_Formula for clue delivery! CTOnews.com Alphawave said it has taped out one of the first chips in the industry to use TSMC N3E manufacturing technology (the second generation of 3-nanometer process nodes). The chip, which has been produced by TSMC and successfully passed all necessary tests, will be showcased at TSMC's OIP forum later this week.

The chip is the Alphawave IP ZeusCORE100 1-112Gbps NRZ / PAM4 Serialer-Deseralizer (SerDes) and supports numerous standards that will be popular in the coming years, including 800G Ethernet, OIF 112G-CEI, PCIe 6.0 and CXL3.0. SerDes is said to support ultra-long channels, providing flexible connectivity solutions for next-generation servers.

Tony Pialis, President and CEO of Alphawave IPAlphawave, said: "Alphawave is honored to be one of the first companies to leverage TSMC's most advanced 3-nanometer technology. Our partnership will continue to bring innovative high-speed connectivity technologies to power state-of-the-art data centers, and we are excited to showcase these solutions at TSMC's OIP Forum event." "

TSMC plans to launch five 3nm process technologies over the next two to three years, with the first-generation 3nm process N3 expected to be used by TSMC's big customer Apple for a handful of designs, while the second-generation 3nm process N3E will have an improved process window, meaning faster yield times, higher performance and lower power consumption.

The N3E is expected to be more widely adopted than the N3, but its mass production is scheduled to begin in mid-2023 or the third quarter of 2023, about a year after TSMC starts high volume manufacturing (HVM) using its N3 production node.

CTOnews.com understands that after TSMC starts N3E HVM next year, it plans to offer three more 3-nanometer nodes, including N3P for performance, N3S for chips requiring high transistor density, and N3X for applications requiring high performance, such as microprocessors.

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