Shulou(Shulou.com)11/24 Report--

CTOnews.com, Oct. 13, TheLec reported that Samsung is planning to use a technology called back Power Network (BSPDN) to develop 2nm, which is actually a new technology launched by researcher Park Byung-jae on Samsung SEDEX 2022 last week.

Simply put, this solution gives another direction in addition to process indentation and 3D packaging: developing the back of the wafer.

Park said that in the contract manufacturing market, technology is evolving from high-k metal gate plane FET to FinFET to MBCFET and now BSPDN.

FinFET (used to be called 3D transistor), which is mainly used at the present stage, is the key chip design technology in the development of 10nm process. It uses a three-sided covered gate design, which can surround the current channel on three sides, so as to reduce current leakage (electronic leakage). But the development of 5nm and even 3nm technology means that FinFET will be out of date, so the industry has developed a four-sided full gate or GAA technology.

The factory then adds what it calls nanowires instead of nanowires, and calls the technology MBCFET. But the BSPDN we are talking about here is different and can be understood as the evolution of the small chip design used by Samsung, Intel and TSMC.

With the help of the small chip technology solution, we can apply the same process on a single chip, or we can connect a variety of chips made by different processes from different manufacturers. This is also the technology solution adopted by Intel 14-generation Courier and AMD Ruilong, which is also known as 3D-SoC, which can combine logic circuits and memory modules at the same time.

According to reports, BSPDN is different from the front-end power supply network, it mainly uses the back-end; the front will have a logic function, while the back will be used for power supply or signal routing.

CTOnews.com learned that the concept of BSPDN was first proposed on IMEC in 2019, when a 2nm paper citing the technology was also published in the 2021 IEDM.

In this Korean paper entitled "SRAM Macro and logical Design and Optimization of back-end Interconnection using 2nm process", the author proposes to move functions such as power supply network to the back of the chip, so as to solve the problem of wiring congestion caused by using only the front. It is said that compared with FSPDN, the performance of BSPDN can be improved by 44% and the power efficiency can be improved by 30%.

"small chips involve small chips that are designed and processed separately," said Eric Beyne, senior researcher at Imec, vice president of research and development, and director of the 3D system integration project. A well-known example is high bandwidth memory (HBM), that is, the stack of dynamic random access memory (DRAM) chips. The memory stack is connected to the processor chip through an interface bus, which limits their use to delay-tolerant applications. As a result, the small chip concept will never allow fast access between logic and fast, primary, and intermediate cache memory. "

With 3D-SOC integration we can use direct and short interconnections to achieve logical memory partitioning thus significantly improving performance. In this paper, the author shows the optimized implementation of the 3D-SOC design, with the memory macro at the top of the Die and the rest of the logic at the bottom of the Die-40% more frequently than the 2D design.

One possible partition of a high-performance 3D-SOC system involves placing some or all of the memory macros on top of the Die and logic at the bottom of the Die.

In terms of technology, this can be achieved by using low-temperature wafer-to-wafer bonding technology to bond the active front of the "logic wafer" to the active front of the "memory wafer". In this configuration, the original backfaces of both wafers are now located outside the 3D-SOC system.

"We can now consider using the 'free' back of these chips to route signals or directly power transistors in 'logic wafers'," Eric Beyne said. Traditionally, signal routing and power transmission take place on the front of the wafer, and they compete for space in complex back-end interconnection schemes. In these designs, the back of the wafer is used only as a carrier. In 2019, Arm's simulation showed for the first time the beneficial impact of using BSPDN in CPU) design, and CPU implemented the 3nm process developed by imec. In this design, the interconnect metal located on the back of the wafer thinning is connected to the 3nm transistor on the front of the wafer using a silicon through hole (TSV) located on the buried power rail.

Therefore, additional performance improvements can be expected when implementing a BSPDN to provide a power-consuming core logic circuit located at the bottom of the "logical memory" 3D-SOC. Alternative 3D-SOC partitions can also be considered, where some memory blocks (such as L1-level cache static random access memory (SRAM)) are also located in the bottom bare chip and are also powered by the back.

In addition to the possibility of extending the 3D-SOC design, BSPDN is also proposed for single-chip logic and SRAM system-on-chip (SOC), which can help with further device and IC extensions.

Geert Van der Plas, imec project manager, said: "moving the power supply network to the back of the silicon wafer has proven to be an interesting way to solve the line back-end (BEOL) routing congestion challenges and reduce the IR voltage drop. The main difference from the 3D-SOC approach is that pseudo-wafers are now bonded to the target wafers to achieve back wafer thinning and metallization." One of imec's partners announced at that time that it would implement such a BSPDN concept in one of its future node chips.

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