Shulou(Shulou.com)11/24 Report--

This article comes from the official account of Wechat: programming Technology Universe (ID:xuanyuancoding), author: Xuanyuan Wind

Ah Q, hurry back. Huzi in the No.2 workshop next door said that we changed their data and came to make trouble.

Due to the sudden appearance of Lao K, I had to end my communication with Xiao Hei ahead of time and rushed back to the No.1 workshop of CPU.

When he saw me coming back, Huzi immediately shouted to me, "what's the matter with you?" it took only a few nanoseconds to change the data for me. What do you think we should do about it? "

I listened in a daze and said again and again, "Tiger, don't worry. I just got back. What's going on? let me understand first, will you?"

Next, Lao K told me what had happened. It turned out that the threads responsible for each of our two CPU workshops were performing an iTunes + operation, and we both put the value of I in our own cache. After that, we did not notify each other, but added it twice but only once, resulting in data inconsistency.

After the atomic operation knew what had happened, I said to Huzi, "everyone executes the same code, and we can't blame it."

Huzi was anxious. "Why don't you blame you? we found the memory and took it away before you. Then you'll have to wait until we finish adding it. If you don't believe it, you can call the memory guy and see if our No.2 workshop came first."

"all right, just calm down. You see, we didn't know you went to get it first. Isn't that understandable? besides, now that things have happened, we should sit down together and think of a way to avoid this kind of problem in the future, don't you think?"

Huzi sighed and asked, "then tell me what you can do?"

I continued to say, "you see, we shouldn't be interfered with when we perform iTunes + operations."

"undisturbed?"

"Yes, for example, when Huzi's No. 2 workshop visits I, our No. 1 workshop cannot visit. We need to wait. We will come back after your visit. The very simple method is very useful."

Tiger was stupefied. "isn't that locking? are you trying to blame the programmer for not locking it before doing iTunes +?"

"it is true to add locks, but it is too troublesome for programmers to add locks for such a simple operation. We just have to deal with it internally by CPU."

"how do you plan to achieve internal processing?" Huzi asked.

"this, let me see." Huzi asked about the concrete realization, but I didn't think of this step yet.

At this time, the old K on one side stood out: "I do have an idea. I can find the bus director. He is the commander in charge of coordinating each workshop to use the system bus to access memory. It should not be difficult for him to coordinate in the middle."

Old K woke up the dreamer at once, and then we went to the bus director, and then we discussed a solution: we defined something called atomic operation, which means that this is an undivisible action. Who wants to perform atomic operation, the bus director adds a LOCK# signal to the system bus, and other workshops have to wait until the atomic operation instructions are executed.

We reported this plan to the leader and soon approved it, and then all eight of our workshops worked according to this plan. later, after the programmers replaced the action of iTunes + with atomic operation, the problem could be easily solved.

However, after a period of time, various workshops began to complain: just because one workshop had to perform an atomic operation, let the bus director lock the system bus, and no one in other workshops could access memory and work, seriously affecting work efficiency.

Complaining is complaining that life has to go on before there is a better alternative.

Problems caused by caching, however, it wasn't long before the problem of data inconsistency appeared again.

This time, it is not a matter of addition. Our two workshops have successively modified the values of variables because of their respective caches, but the other side did not know immediately and misused the wrong value, resulting in a big mistake.

"Ah Q, it was a good idea last time, but it couldn't solve the problem this time," Huzi came to the door again.

"you're just in time. I was just about to talk to you about it."

"Oh, yeah, did you think of a way to crack it?"

"it's just some preliminary ideas. the crux of the problem is that now each workshop goes its own way and has its own private cache. After modifying the data, they do not say hello to each other when updating the memory, and there is a lack of a contact mechanism."

Huzi nodded. "indeed, so we need to establish a contact mechanism to manage the cache content in each workshop, right?"

"Yes! it's not up to us. I suggest convening representatives from eight core workshops to hold a meeting to discuss the problem in detail. Oh, by the way, call in the bus director, too. He may be able to provide some ideas with his rich experience."

Cache consistency protocol MESI is very fast, and our eight core workshops of CPU have held a meeting on this issue, and have achieved very important results.

We have led a new dedicated line to connect the eight core workshops for information communication between workshops, which is different from the external bus system of CPU, which is called on-chip bus.

After the new line has been laid, we can communicate instantly through this line. In order to solve the previous problems, we have also developed a set of rules called cache consistency protocol.

The rules specify cache units for all workshops-cache lines have four states:

The modified Modified (M) cache line has been modified and is not the same as the memory value. If another CPU kernel wants to read this piece of data in memory, write the cache line back to main memory before then, changing the state to shared (S).

Exclusive Exclusive (E) cache lines are only in the current CPU core cache and are the same as in-memory data. When another CPU core reads it, the state becomes shared; if the current CPU core modifies it, it becomes modified.

Shared Shared (S) cache lines exist in caches of multiple CPU cores and are consistent with the contents in memory.

Invalid Invalid (I) cache line is invalid

The transition between the four states is as follows:

According to this set of rules, people can no longer be as casual as they used to be. Workshops should communicate with each other when reading and writing their own caches to avoid using outdated data.

In addition, it is stipulated that if a memory area is cached by multiple workshops, many workshops are no longer allowed to modify the cache at the same time.

Another harvest of the meeting was that every atomic operation, which was previously criticized by various workshops, had to lock the bus, and the problem that everyone had to wait for access to memory was also solved. In the future, the bus director no longer needs to lock the bus, which can be done through this cache consistency protocol.

Since then, the problem of data inconsistency has finally been cured, and our 8 workshops can work happily again.

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