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This article comes from the official account of Wechat: programming Technology Universe (ID:xuanyuancoding), author: Xuanyuan Wind O

Interrupt mechanism this is Ah Q from CPU No.1 workshop, here I am again!

Our daily job is to keep executing code instructions, but it's not easy behind what seems to be a simple job.

We can't just do nothing but execute the code and have to deal with other units connected to the motherboard. The ones who keep in touch with each other are keyboards, mice, disks, oh yes, and network cards. This guy has pissed me off recently. We'll talk about it later.

I thought the memory guy was slow enough, but I didn't expect to communicate with the above guys more slowly than him. The time in our CPU factory is worth a lot of money, so we can't wait and waste time. Later, the factory came up with a method called interruption.

A headlight has been installed in our workshop. If these units want to contact us to do something, they will first send us an interrupt signal, and the headlight will turn on automatically. When we are working to execute code instructions, we glance at each instruction to see if the headlights are on. Once you find that the light is on, put aside the work at hand and deal with it.

We have a poor memory, and we have to go back to the original work when we are done. In order to pick it up later, we have to put the values of the registers of the currently executed thread before leaving. Where is the execution, and so on. All this information is stored in the stack of this thread.

But sometimes we don't want to be interrupted by them when we are doing something very important. So we set a mark in the eflags register in the workshop, if it is 1, we are allowed to be interrupted, if it is 0, then even if the king calls us, then we don't care.

Oh no, there is also an unshielded interrupt NMI, which goes through the green channel. But I don't expect that to happen, because there are usually no good things, such as a power outage or a high temperature, or something wrong with the bus.

There is another problem with 8259A PIC. There are many units that work with us. We have to distinguish who came from the message, and it is also a headache if they come to find it together and in what order to deal with it.

To this end, the factory set up a separate wholly-owned subsidiary to take charge of this matter, he is the programmable interrupt controller PIC, nicknamed 8259A, other units want to contact us have to go through this PIC, we only need to dock with PIC.

We all assign a number to the office, which is called the interrupt vector. We also have a table called the interrupt descriptor table IDT, which records a lot of information, including the address of the function that handles the interrupt number. After we find PIC and get the number, we will execute the handler function OK.

This table is a little big, with 256items. our CPU workshop has limited space, so I put it in the guy in memory. in order to find this table quickly, I added a register called idtr to point to this table.

In fact, in addition to interrupts, if we encounter an exception when executing instructions, we will also go to this table to execute exception handling functions, such as divisor 0, memory address error and so on.

In this case, we must take the initiative to let go of our work and handle the exception, so we also say that the exception is synchronous, and the interrupt does not know when it will occur, so it is asynchronous.

APIC8259A did a good job, but then our factory expanded, from single-core CPU to multi-core, he was a little unable to cope.

Finally, one day, the factory held a meeting to withdraw 8259A and set up a new wholly-owned subsidiary called Advanced Programmable interrupt Controller (APIC). The name was added to the word Advanced, and the job was the same.

But don't say, these two words are really not bragging, they are higher than 8259A, I don't know where.

As soon as the new APIC company took office, two departments were set up, one is called I / O APIC, which is responsible for receiving those units that want to work with us, and the other is called Local APIC, which is outsourced to work in various workshops in our CPU, so it is named Local because it is next to us.

After the I / O APIC receives the interrupt signal, it is distributed to the corresponding Local APIC according to its own strategy, and our eight workshops can concentrate on it, which saves us a lot of trouble.

Not only that, through this outsourced team, our eight workshops can also initiate interrupt requests to each other, which we call interprocessor interrupt Inter-Processor Interrupt, or IPI.

Break affinity whenever a packet arrives in the network, the guy on the network card sends an interrupt message telling us to deal with it.

But recently, I don't know why, the amount of data on the Internet has soared. There are obviously eight workshops in our factory, but he only has to send messages to us, so that the work at hand is always interrupted and busy.

Finally, I couldn't help it and went to the guy with the network card to have a theory. But he told me that it was not his fault. Who was responsible for the distribution? APIC was in charge.

When I thought about it, I went to APIC and asked them to share some of it with other workshops.

APIC said they couldn't make the decision and had to let the factory decide.

A few days later, there was a meeting in the factory, attended by representatives of various workshops, responsible persons of APIC, and invited relevant representatives from the operating system.

At the meeting, everyone quarreled over the matter.

Huzi in Workshop 2: "Ah Q, whoever called you Workshop 1 is Bootstrap Processor, you should work harder."

The representative of the No. 3 workshop: "what you said is not appropriate. We are a Team and we should help each other! how about this? since there are so many units to contact us, we will assign workers, for example, the No. 1 workshop is responsible for the network card, the No. 2 is responsible for the disk, our No. 3 is responsible for the keyboard, and so on."

The representative of the No. 5 workshop: "you have a beautiful idea. How many interrupts can the keyboard send in a day and how many interrupts can the network card send in a day? you just choose to do it easily." well, what do you think of random distribution for load balancing? "

The representative of the eighth workshop: "what a random thing? what a hassle. In my opinion, our eight workshops will come in turn."

At this time, the leader asked the operating system representative if he had any suggestions.

This stands up, pushes his glasses and says, "have you ever heard of the CPU affinity of threads?"

Everyone shook their heads and asked, "what does that mean?"

"that is, some threads want to be bound to one of your cores and do not want to execute in this core and that core."

I accepted his words: "there seems to be such a thing. I have encountered a thread that has been assigned to our No.1 workshop all the time, but we don't have to care about this. Who is not working? it's the same to us."

The representative shook his head. "Oh, this is different!" You manage the first and second level cache of each core by yourself. if you switch to another core, the cache will probably be useless and will have to be re-established. They don't care about ordinary threads, but if some threads perform a lot of memory access and operations and have high performance requirements, they will be very concerned about this problem. "

All of us suddenly realized and nodded one after another.

Huzi stood up and asked, "so how did you achieve this affinity? what does this have to do with our meeting today?"

The representative continued, "Let me answer your first question. Thread scheduling is the work done by our operating system. We provide API interfaces, and threads show their affinity by calling these interfaces, and we can assign threads to you to execute as they wish."

The representative took a sip of water and then said, "I'll answer your second question. Since threads can have affinity, interrupts can also be distributed in this way! APIC has a distribution policy by default, but it also provides affinity settings to specify which cores to handle. Wouldn't it be better if you don't have to fix the rules and be flexible?"

Just finished, a young boy suddenly appeared at the door of the conference room and waved the operating system representative out.

Next, we discussed the feasibility of this scheme in detail, and finally we unanimously decided to do so. We proposed a thing called interrupt affinity. The operating system provides a configurable entry smp_affinity, which can decide who handles the interrupt by setting the mask of each processor core, and APIC goes back to be responsible for landing support.

With this plan, and then encounter the network peak, the pressure of our No.1 workshop will have a way to alleviate.

We had just reached an agreement when the operating system representative returned to the conference room and said solemnly, "Sorry, everyone, there is something that needs to be taken care of in the operating system. Let's go first."

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